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Searched refs:dram_pll_cfg0 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx8m/
Dclock.c127 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0); in decode_sscg_pll()
532 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; in dram_pll_init()
/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dimx-regs.h231 u32 dram_pll_cfg0; member