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Searched refs:dram_timing2 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dsdram_gen5.h27 u32 dram_timing2; member
86 u32 dram_timing2; member
/external/u-boot/drivers/ddr/altera/
Dsdram_gen5.c337 writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); in sdr_load_regs()
/external/u-boot/arch/arm/mach-socfpga/
Dwrap_sdram_config.c46 .dram_timing2 =