/external/llvm/test/MC/Mips/ |
D | rotations64.s | 111 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a] 131 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa] 136 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a] 139 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a] 159 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa] 164 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a] 182 # CHECK-64R: drotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x7a] 185 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a] 190 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a] 195 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa] [all …]
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D | mips_directives.s | 76 # CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba] 78 drotr $9, $6, 30
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D | mips64-alu-instructions.s | 76 # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00] 101 drotr $9, $6, 20
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
D | rotations64.s | 111 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a] 131 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa] 136 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a] 139 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a] 159 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa] 164 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a] 182 # CHECK-64R: drotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x7a] 185 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a] 190 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a] 195 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa] [all …]
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D | mips_directives.s | 77 # CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba] 79 drotr $9, $6, 30
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D | mips64-alu-instructions.s | 76 # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00] 101 drotr $9, $6, 20
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
D | mips64shift.ll | 90 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 99 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
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/external/llvm/test/CodeGen/Mips/ |
D | mips64shift.ll | 91 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 100 ; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
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/external/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 15 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 16 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 15 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 16 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/capstone/suite/MC/Mips/ |
D | mips64-alu-instructions.s.cs | 38 0x3a,0x4d,0x26,0x00 = drotr $9, $6, 20
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/external/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 14 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 15 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 14 …drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe… 15 …drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm/test/MC/Mips/mips64r5/ |
D | valid.s | 96 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x… 97 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
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/external/llvm/test/MC/Mips/mips64r2/ |
D | valid.s | 96 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x… 97 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
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/external/llvm/test/MC/Mips/mips64r3/ |
D | valid.s | 96 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x… 97 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
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/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
D | mips64shift.ll | 88 ; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r5/ |
D | valid.s | 136 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x… 137 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r3/ |
D | valid.s | 136 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x… 137 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r2/ |
D | valid.s | 142 …drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0x… 143 …drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0x…
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/external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
D | valid-mips64r2-el.txt | 125 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15 126 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15 272 0xba 0xa1 0x3b 0x00 # CHECK: drotr $20, $27, 6
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r2/ |
D | valid-mips64r2-el.txt | 126 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15 127 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15 277 0xba 0xa1 0x3b 0x00 # CHECK: drotr $20, $27, 6
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/external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
D | valid-mips64r5-el.txt | 122 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15 123 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
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/external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
D | valid-mips64r3-el.txt | 122 0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15 123 0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
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/external/llvm/lib/Target/Mips/ |
D | MicroMips64r6InstrInfo.td | 60 class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>; 258 class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
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