| /external/jemalloc_new/include/jemalloc/internal/ |
| D | log.h | 95 size_t dst_offset = 0; in log_impl_varargs() local
96 dst_offset += malloc_snprintf(buf, JEMALLOC_LOG_BUFSIZE, "%s: ", name); in log_impl_varargs()
97 dst_offset += malloc_vsnprintf(buf + dst_offset, in log_impl_varargs()
98 JEMALLOC_LOG_BUFSIZE - dst_offset, format, ap); in log_impl_varargs()
99 dst_offset += malloc_snprintf(buf + dst_offset, in log_impl_varargs()
100 JEMALLOC_LOG_BUFSIZE - dst_offset, "\n"); in log_impl_varargs()
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| /external/adhd/cras/src/server/ |
| D | linear_resampler.c | 24 unsigned int dst_offset; member
61 lr->dst_offset = 0; in linear_resampler_set_rates()
84 in_frames = (float)(lr->dst_offset + frames) / lr->f; in linear_resampler_out_frames_to_in()
99 if (out_frames > lr->dst_offset) in linear_resampler_in_frames_to_out()
100 return 1 + (unsigned int)(out_frames - lr->dst_offset); in linear_resampler_in_frames_to_out()
130 src_pos = (float)(lr->dst_offset + dst_idx) / lr->f; in linear_resampler_resample()
165 lr->dst_offset += dst_idx; in linear_resampler_resample()
167 (lr->dst_offset > lr->to_times_100)) { in linear_resampler_resample()
169 lr->dst_offset -= lr->to_times_100; in linear_resampler_resample()
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| D | cras_audio_area.c | 26 unsigned int dst_offset, in cras_audio_area_copy() argument
36 ncopy = MIN(src->frames - src_offset, dst->frames - dst_offset); in cras_audio_area_copy()
49 dst_offset * dst->channels[dst_idx].step_bytes; in cras_audio_area_copy()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | evergreen_hw_context.c | 34 uint64_t dst_offset, in evergreen_dma_copy_buffer() argument
46 util_range_add(&rdst->valid_buffer_range, dst_offset, in evergreen_dma_copy_buffer()
47 dst_offset + size); in evergreen_dma_copy_buffer()
49 dst_offset += rdst->gpu_address; in evergreen_dma_copy_buffer()
53 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) { in evergreen_dma_copy_buffer()
72 radeon_emit(cs, dst_offset & 0xffffffff); in evergreen_dma_copy_buffer()
74 radeon_emit(cs, (dst_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
76 dst_offset += csize << shift; in evergreen_dma_copy_buffer()
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| D | r600_hw_context.c | 489 struct pipe_resource *dst, uint64_t dst_offset, in r600_cp_dma_copy_buffer() argument
501 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, in r600_cp_dma_copy_buffer()
502 dst_offset + size); in r600_cp_dma_copy_buffer()
504 dst_offset += r600_resource(dst)->gpu_address; in r600_cp_dma_copy_buffer()
541 radeon_emit(cs, dst_offset); /* DST_ADDR_LO [31:0] */ in r600_cp_dma_copy_buffer()
542 radeon_emit(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */ in r600_cp_dma_copy_buffer()
552 dst_offset += byte_count; in r600_cp_dma_copy_buffer()
571 uint64_t dst_offset, in r600_dma_copy_buffer() argument
583 util_range_add(&rdst->valid_buffer_range, dst_offset, in r600_dma_copy_buffer()
584 dst_offset + size); in r600_dma_copy_buffer()
[all …]
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| /external/mesa3d/src/gallium/auxiliary/draw/ |
| D | draw_pt_fetch.c | 68 unsigned dst_offset = 0; in draw_pt_fetch_prepare() local
77 dst_offset = offsetof(struct vertex_header, data); in draw_pt_fetch_prepare()
92 key.element[nr].output_offset = dst_offset; in draw_pt_fetch_prepare()
94 dst_offset += sizeof(uint); in draw_pt_fetch_prepare()
102 key.element[nr].output_offset = dst_offset; in draw_pt_fetch_prepare()
105 dst_offset += 4 * sizeof(int); in draw_pt_fetch_prepare()
113 key.element[nr].output_offset = dst_offset; in draw_pt_fetch_prepare()
116 dst_offset += 4 * sizeof(unsigned); in draw_pt_fetch_prepare()
124 key.element[nr].output_offset = dst_offset; in draw_pt_fetch_prepare()
127 dst_offset += 4 * sizeof(float); in draw_pt_fetch_prepare()
[all …]
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| D | draw_pt_emit.c | 60 unsigned dst_offset; in draw_pt_emit_prepare() local
81 dst_offset = 0; in draw_pt_emit_prepare()
110 hw_key.element[i].output_offset = dst_offset; in draw_pt_emit_prepare()
112 dst_offset += emit_sz; in draw_pt_emit_prepare()
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| /external/mesa3d/src/gallium/drivers/i915/ |
| D | i915_blit.c | 41 unsigned dst_offset, in i915_fill_blit() argument
50 __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h); in i915_fill_blit()
82 OUT_RELOC_FENCED(dst_buffer, I915_USAGE_2D_TARGET, dst_offset); in i915_fill_blit()
96 unsigned dst_offset, in i915_copy_blit() argument
111 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); in i915_copy_blit()
154 OUT_RELOC_FENCED(dst_buffer, I915_USAGE_2D_TARGET, dst_offset); in i915_copy_blit()
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| D | i915_blit.h | 40 unsigned dst_offset,
50 unsigned dst_offset,
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_blit.c | 270 uint32_t dst_offset, dst_tile_x, dst_tile_y; in emit_miptree_blit() local
273 &dst_offset, &dst_tile_x, &dst_tile_y); in emit_miptree_blit()
282 dst_mt->bo, dst_mt->offset + dst_offset, in emit_miptree_blit()
525 GLuint dst_offset, in intelEmitCopyBlit() argument
559 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); in intelEmitCopyBlit()
589 if (!alignment_valid(brw, dst_offset, dst_tiling)) in intelEmitCopyBlit()
598 dst_pitch % 4 != 0 || dst_offset % cpp != 0) in intelEmitCopyBlit()
627 OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset); in intelEmitCopyBlit()
629 OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset); in intelEmitCopyBlit()
653 GLuint dst_offset, in intelEmitImmediateColorExpandBlit() argument
[all …]
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| D | intel_blit.h | 40 GLuint dst_offset,
75 GLuint dst_offset,
82 unsigned int dst_offset,
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_dma.c | 32 uint64_t dst_offset, in si_dma_copy_buffer() argument
44 util_range_add(&rdst->valid_buffer_range, dst_offset, in si_dma_copy_buffer()
45 dst_offset + size); in si_dma_copy_buffer()
47 dst_offset += rdst->gpu_address; in si_dma_copy_buffer()
51 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) { in si_dma_copy_buffer()
68 radeon_emit(cs, dst_offset); in si_dma_copy_buffer()
70 radeon_emit(cs, (dst_offset >> 32UL) & 0xff); in si_dma_copy_buffer()
72 dst_offset += count; in si_dma_copy_buffer()
297 uint64_t dst_offset, src_offset; in si_dma_copy() local
306 dst_offset = rdst->surface.u.legacy.level[dst_level].offset; in si_dma_copy()
[all …]
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| D | si_cp_dma.c | 401 uint64_t dst_offset, uint64_t src_offset, unsigned size, in si_copy_buffer() argument
414 if (dst != src || dst_offset != src_offset) { in si_copy_buffer()
418 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, in si_copy_buffer()
419 dst_offset + size); in si_copy_buffer()
422 dst_offset += r600_resource(dst)->gpu_address; in si_copy_buffer()
453 main_dst_offset = dst_offset + skipped_size; in si_copy_buffer()
480 si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size, in si_copy_buffer()
493 if (dst_offset != src_offset) in si_copy_buffer()
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_blit.c | 225 GLuint dst_offset, in intelEmitCopyBlit() argument
241 if (dst_offset & 4095) in intelEmitCopyBlit()
271 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); in intelEmitCopyBlit()
277 dst_pitch % 4 != 0 || dst_offset % cpp != 0) in intelEmitCopyBlit()
327 dst_offset); in intelEmitCopyBlit()
522 GLuint dst_offset, in intelEmitImmediateColorExpandBlit() argument
532 if (dst_offset & 4095) in intelEmitImmediateColorExpandBlit()
546 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); in intelEmitImmediateColorExpandBlit()
571 dst_offset); in intelEmitImmediateColorExpandBlit()
595 unsigned int dst_offset, in intel_emit_linear_blit() argument
[all …]
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| D | intel_pixel_read.c | 80 GLuint dst_offset; in do_blit_readpixels() local
114 dst_offset = (GLintptr)pixels; in do_blit_readpixels()
115 dst_offset += _mesa_image_offset(2, pack, width, height, in do_blit_readpixels()
135 dst_offset, in do_blit_readpixels()
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| D | intel_blit.h | 47 GLuint dst_offset,
71 GLuint dst_offset,
78 unsigned int dst_offset,
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| /external/mesa3d/src/intel/vulkan/ |
| D | genX_gpu_memcpy.c | 56 struct anv_bo *dst, uint32_t dst_offset, in genX()
62 assert(dst_offset % 4 == 0); in genX()
69 (struct anv_address) { dst, dst_offset + i}; in genX()
96 struct anv_bo *dst, uint32_t dst_offset, in genX()
103 assert(dst_offset + size <= dst->size); in genX()
109 bs = gcd_pow2_u64(bs, dst_offset); in genX()
201 sob.SurfaceBaseAddress = (struct anv_address) { dst, dst_offset }; in genX()
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| /external/v8/src/ |
| D | intl.cc | 376 int32_t* raw_offset, int32_t* dst_offset) { in GetOffsets() argument
389 GetTimeZone()->getOffset(time_ms, false, *raw_offset, *dst_offset, status); in GetOffsets()
394 *dst_offset, status); in GetOffsets()
401 int32_t raw_offset, dst_offset; in DaylightSavingsOffset() local
402 if (!GetOffsets(time_ms, true, &raw_offset, &dst_offset)) return 0; in DaylightSavingsOffset()
403 return dst_offset; in DaylightSavingsOffset()
407 int32_t raw_offset, dst_offset; in LocalTimeOffset() local
408 if (!GetOffsets(time_ms, is_utc, &raw_offset, &dst_offset)) return 0; in LocalTimeOffset()
409 return raw_offset + dst_offset; in LocalTimeOffset()
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| /external/tensorflow/tensorflow/lite/toco/graph_transformations/ |
| D | resolve_constant_pack.cc | 38 int dst_offset = 0; in Pack() local
43 memcpy(&output_data[dst_offset], &input_array.GetBuffer<Type>().data[0], in Pack()
45 dst_offset += input_size; in Pack()
47 CHECK_EQ(dst_offset, output_data.size()); in Pack()
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| D | resolve_constant_strided_slice.cc | 74 for (size_t dst_offset = 0; dst_offset < output_data.size(); ++dst_offset) { in StridedSlice() local
76 output_data[dst_offset] = input_buffer.data[Offset(input_shape, src_coord)]; in StridedSlice()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_pixel_read.c | 101 intptr_t dst_offset; in do_blit_readpixels() local
143 dst_offset = 0; in do_blit_readpixels()
148 dst_offset = (intptr_t)pixels; in do_blit_readpixels()
168 dst_offset, in do_blit_readpixels()
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| D | radeon_tex_copy.c | 85 intptr_t dst_offset = radeon_miptree_image_offset(timg->mt, face, level); in do_copy_texsubimage() local
90 fprintf(stderr, "to: x %d, y %d, offset %d\n", dstx, dsty, (uint32_t) dst_offset); in do_copy_texsubimage()
130 timg->mt->bo, dst_offset, dst_mesaformat, in do_copy_texsubimage()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_pixel_read.c | 101 intptr_t dst_offset; in do_blit_readpixels() local
143 dst_offset = 0; in do_blit_readpixels()
148 dst_offset = (intptr_t)pixels; in do_blit_readpixels()
168 dst_offset, in do_blit_readpixels()
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| D | radeon_tex_copy.c | 85 intptr_t dst_offset = radeon_miptree_image_offset(timg->mt, face, level); in do_copy_texsubimage() local
90 fprintf(stderr, "to: x %d, y %d, offset %d\n", dstx, dsty, (uint32_t) dst_offset); in do_copy_texsubimage()
130 timg->mt->bo, dst_offset, dst_mesaformat, in do_copy_texsubimage()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_meta_resolve_cs.c | 119 …nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_con… in build_resolve_compute_shader() local
120 nir_intrinsic_set_base(dst_offset, 0); in build_resolve_compute_shader()
121 nir_intrinsic_set_range(dst_offset, 16); in build_resolve_compute_shader()
122 dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8)); in build_resolve_compute_shader()
123 dst_offset->num_components = 2; in build_resolve_compute_shader()
124 nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset"); in build_resolve_compute_shader()
125 nir_builder_instr_insert(&b, &dst_offset->instr); in build_resolve_compute_shader()
137 nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa); in build_resolve_compute_shader()
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