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Searched refs:dst_queue_mask (Results 1 – 2 of 2) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_meta_copy.c373 uint32_t dst_queue_mask = radv_image_queue_family_mask(dest_image, in meta_copy_image() local
376 bool dst_compressed = radv_layout_dcc_compressed(dest_image, dest_image_layout, dst_queue_mask); in meta_copy_image()
Dradv_cmd_buffer.c3920 unsigned dst_queue_mask, in radv_handle_depth_image_transition() argument
3932 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) { in radv_handle_depth_image_transition()
3936 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) { in radv_handle_depth_image_transition()
3940 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) { in radv_handle_depth_image_transition()
3976 unsigned dst_queue_mask, in radv_handle_cmask_image_transition() argument
3985 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) { in radv_handle_cmask_image_transition()
4011 unsigned dst_queue_mask, in radv_handle_dcc_image_transition() argument
4018 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ? in radv_handle_dcc_image_transition()
4021 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) { in radv_handle_dcc_image_transition()
4024 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) { in radv_handle_dcc_image_transition()
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