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Searched refs:dv_pll0_regs (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-davinci/
Ddm365_lowlevel.c30 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); in dm365_pll1_init()
32 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
33 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
40 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC); in dm365_pll1_init()
43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
53 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
56 writel(pllmult, &dv_pll0_regs->pllm); in dm365_pll1_init()
57 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
61 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); in dm365_pll1_init()
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/external/u-boot/arch/arm/mach-davinci/include/mach/
Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro