Searched refs:dx0gcr (Results 1 – 7 of 7) sorted by relevance
120 clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000); in mctl_init()141 clrbits_le32(&mctl_phy->dx0gcr, 0x600); in mctl_init()
150 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); in mctl_channel_init()
124 u32 dx0gcr; member
200 u32 dx0gcr; /* 0x1c0 Byte lane 0 General Configuration*/ member
132 DDRPHY_REG_REG(dx0gcr),
227 u32 dx0gcr; /* 0x1c0 */ member
214 u32 dx0gcr; /* 0x1c0 */ member