Searched refs:dx1gcr (Results 1 – 7 of 7) sorted by relevance
121 clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000); in mctl_init()142 clrbits_le32(&mctl_phy->dx1gcr, 0x600); in mctl_init()245 writel(0, &mctl_phy->dx1gcr); in mctl_init()
151 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); in mctl_channel_init()
125 u32 dx1gcr; member
207 u32 dx1gcr; /* 0x200 Byte lane 1 General Configuration*/ member
133 DDRPHY_REG_REG(dx1gcr),
242 u32 dx1gcr; /* 0x200 */ member
221 u32 dx1gcr; /* 0x200 */ member