Searched refs:eltsize (Results 1 – 4 of 4) sorted by relevance
| /external/elfutils/libdw/ |
| D | dwarf_aggregate_size.c | 56 Dwarf_Word eltsize; in array_size() local
58 if (aggregate_size (get_type (die, attr_mem, &type_mem), &eltsize, in array_size()
152 Dwarf_Word stride = eltsize; in array_size()
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| /external/llvm/test/MC/Disassembler/X86/ |
| D | avx-512.txt | 82 # TupleType = T1S, 64-bit eltsize
86 # TupleType = T1S, 32-bit eltsize
94 # TupleType = FV, broadcast, 64-bit eltsize
98 # TupleType = FV, broadcast, 32-bit eltsize
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/X86/ |
| D | avx-512.txt | 86 # TupleType = T1S, 64-bit eltsize
90 # TupleType = T1S, 32-bit eltsize
98 # TupleType = FV, broadcast, 64-bit eltsize
102 # TupleType = FV, broadcast, 32-bit eltsize
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 496 class TypedVecListAsmOperand<int count, string vecty, int lanes, int eltsize>
498 let Name = "TypedVectorList" # count # "_" # lanes # eltsize;
501 = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
505 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>
507 # eltsize # "'>">;
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