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Searched refs:fctidz (Results 1 – 25 of 26) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Di64_fp.ll7 ; RUN: grep fctidz
11 ; RUN: grep fctidz
15 ; RUN: not grep fctidz
19 ; RUN: not grep fctidz
/external/llvm/test/CodeGen/PowerPC/
Di64_fp.ll7 ; RUN: grep fctidz
11 ; RUN: grep fctidz
15 ; RUN: not grep fctidz
19 ; RUN: not grep fctidz
Dfp-to-int-to-fp.ll14 ; FPCVT: fctidz [[REG1:[0-9]+]], 1
19 ; PPC64: fctidz [[REG1:[0-9]+]], 1
33 ; FPCVT: fctidz [[REG1:[0-9]+]], 1
38 ; PPC64: fctidz [[REG1:[0-9]+]], 1
Dfast-isel-conversion-p5.ll74 ; ELF64: fctidz
98 ; ELF64: fctidz
112 ; ELF64: fctidz
124 ; ELF64: fctidz
Dfast-isel-conversion.ll405 ; ELF64: fctidz
408 ; ELF64LE: fctidz
411 ; PPC970: fctidz
445 ; ELF64: fctidz
448 ; ELF64LE: fctidz
451 ; PPC970: fctidz
473 ; PPC970: fctidz
511 ; PPC970: fctidz
Dpr26180.ll9 ; CHECK: fctidz 1, 1
Dfloat-to-int.ll12 ; CHECK: fctidz [[REG:[0-9]+]], 1
29 ; CHECK: fctidz [[REG:[0-9]+]], 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Di64_fp.ll7 ; RUN: grep fctidz
11 ; RUN: grep fctidz
15 ; RUN: not grep fctidz
19 ; RUN: not grep fctidz
Dfast-isel-conversion-p5.ll74 ; ELF64: fctidz
98 ; ELF64: fctidz
112 ; ELF64: fctidz
124 ; ELF64: fctidz
Dfp-to-int-to-fp.ll18 ; PPC64: fctidz [[REG1:[0-9]+]], 1
36 ; PPC64: fctidz [[REG1:[0-9]+]], 1
Dfast-isel-conversion.ll343 ; CHECK: fctidz
346 ; PPC970: fctidz
376 ; CHECK: fctidz
379 ; PPC970: fctidz
397 ; PPC970: fctidz
428 ; PPC970: fctidz
Dpr26180.ll9 ; CHECK: fctidz 1, 1
Dfloat-to-int.ll17 ; CHECK: fctidz [[REG:[0-9]+]], 1
40 ; CHECK: fctidz [[REG:[0-9]+]], 1
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-fp.s.cs79 0xfc,0x40,0x1e,0x5e = fctidz 2, 3
80 0xfc,0x40,0x1e,0x5f = fctidz. 2, 3
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s258 # CHECK-BE: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e]
259 # CHECK-LE: fctidz 2, 3 # encoding: [0x5e,0x1e,0x40,0xfc]
260 fctidz 2, 3
261 # CHECK-BE: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f]
262 # CHECK-LE: fctidz. 2, 3 # encoding: [0x5f,0x1e,0x40,0xfc]
263 fctidz. 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s272 # CHECK-BE: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e]
273 # CHECK-LE: fctidz 2, 3 # encoding: [0x5e,0x1e,0x40,0xfc]
274 fctidz 2, 3
275 # CHECK-BE: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f]
276 # CHECK-LE: fctidz. 2, 3 # encoding: [0x5f,0x1e,0x40,0xfc]
277 fctidz. 2, 3
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-fp.txt234 # CHECK: fctidz 2, 3
237 # CHECK: fctidz. 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-fp.txt240 # CHECK: fctidz 2, 3
243 # CHECK: fctidz. 2, 3
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCSchedule.td176 // fctidz FPGeneral
DPPCInstr64Bit.td672 "fctidz $frD, $frB", FPGeneral,
/external/v8/src/ppc/
Dassembler-ppc.h1235 void fctidz(const DoubleRegister frt, const DoubleRegister frb,
Dconstants-ppc.h1501 V(fctidz, FCTIDZ, 0xFC00065E) \
Dassembler-ppc.cc1863 void Assembler::fctidz(const DoubleRegister frt, const DoubleRegister frb, in fctidz() function in v8::internal::Assembler
Dmacro-assembler-ppc.cc726 fctidz(double_dst, double_input); in ConvertDoubleToInt64()
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td1156 "fctidz", "$frD, $frB", IIC_FPGeneral,

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