/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
D | i64_fp.ll | 7 ; RUN: grep fctidz 11 ; RUN: grep fctidz 15 ; RUN: not grep fctidz 19 ; RUN: not grep fctidz
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/external/llvm/test/CodeGen/PowerPC/ |
D | i64_fp.ll | 7 ; RUN: grep fctidz 11 ; RUN: grep fctidz 15 ; RUN: not grep fctidz 19 ; RUN: not grep fctidz
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D | fp-to-int-to-fp.ll | 14 ; FPCVT: fctidz [[REG1:[0-9]+]], 1 19 ; PPC64: fctidz [[REG1:[0-9]+]], 1 33 ; FPCVT: fctidz [[REG1:[0-9]+]], 1 38 ; PPC64: fctidz [[REG1:[0-9]+]], 1
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D | fast-isel-conversion-p5.ll | 74 ; ELF64: fctidz 98 ; ELF64: fctidz 112 ; ELF64: fctidz 124 ; ELF64: fctidz
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D | fast-isel-conversion.ll | 405 ; ELF64: fctidz 408 ; ELF64LE: fctidz 411 ; PPC970: fctidz 445 ; ELF64: fctidz 448 ; ELF64LE: fctidz 451 ; PPC970: fctidz 473 ; PPC970: fctidz 511 ; PPC970: fctidz
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D | pr26180.ll | 9 ; CHECK: fctidz 1, 1
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D | float-to-int.ll | 12 ; CHECK: fctidz [[REG:[0-9]+]], 1 29 ; CHECK: fctidz [[REG:[0-9]+]], 1
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
D | i64_fp.ll | 7 ; RUN: grep fctidz 11 ; RUN: grep fctidz 15 ; RUN: not grep fctidz 19 ; RUN: not grep fctidz
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D | fast-isel-conversion-p5.ll | 74 ; ELF64: fctidz 98 ; ELF64: fctidz 112 ; ELF64: fctidz 124 ; ELF64: fctidz
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D | fp-to-int-to-fp.ll | 18 ; PPC64: fctidz [[REG1:[0-9]+]], 1 36 ; PPC64: fctidz [[REG1:[0-9]+]], 1
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D | fast-isel-conversion.ll | 343 ; CHECK: fctidz 346 ; PPC970: fctidz 376 ; CHECK: fctidz 379 ; PPC970: fctidz 397 ; PPC970: fctidz 428 ; PPC970: fctidz
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D | pr26180.ll | 9 ; CHECK: fctidz 1, 1
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D | float-to-int.ll | 17 ; CHECK: fctidz [[REG:[0-9]+]], 1 40 ; CHECK: fctidz [[REG:[0-9]+]], 1
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/external/capstone/suite/MC/PowerPC/ |
D | ppc64-encoding-fp.s.cs | 79 0xfc,0x40,0x1e,0x5e = fctidz 2, 3 80 0xfc,0x40,0x1e,0x5f = fctidz. 2, 3
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/external/llvm/test/MC/PowerPC/ |
D | ppc64-encoding-fp.s | 258 # CHECK-BE: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e] 259 # CHECK-LE: fctidz 2, 3 # encoding: [0x5e,0x1e,0x40,0xfc] 260 fctidz 2, 3 261 # CHECK-BE: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f] 262 # CHECK-LE: fctidz. 2, 3 # encoding: [0x5f,0x1e,0x40,0xfc] 263 fctidz. 2, 3
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
D | ppc64-encoding-fp.s | 272 # CHECK-BE: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e] 273 # CHECK-LE: fctidz 2, 3 # encoding: [0x5e,0x1e,0x40,0xfc] 274 fctidz 2, 3 275 # CHECK-BE: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f] 276 # CHECK-LE: fctidz. 2, 3 # encoding: [0x5f,0x1e,0x40,0xfc] 277 fctidz. 2, 3
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/external/llvm/test/MC/Disassembler/PowerPC/ |
D | ppc64-encoding-fp.txt | 234 # CHECK: fctidz 2, 3 237 # CHECK: fctidz. 2, 3
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
D | ppc64-encoding-fp.txt | 240 # CHECK: fctidz 2, 3 243 # CHECK: fctidz. 2, 3
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCSchedule.td | 176 // fctidz FPGeneral
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D | PPCInstr64Bit.td | 672 "fctidz $frD, $frB", FPGeneral,
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/external/v8/src/ppc/ |
D | assembler-ppc.h | 1235 void fctidz(const DoubleRegister frt, const DoubleRegister frb,
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D | constants-ppc.h | 1501 V(fctidz, FCTIDZ, 0xFC00065E) \
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D | assembler-ppc.cc | 1863 void Assembler::fctidz(const DoubleRegister frt, const DoubleRegister frb, in fctidz() function in v8::internal::Assembler
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D | macro-assembler-ppc.cc | 726 fctidz(double_dst, double_input); in ConvertDoubleToInt64()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstr64Bit.td | 1156 "fctidz", "$frD, $frB", IIC_FPGeneral,
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