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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Darm-vmrs_vmsr.txt19 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
20 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
21 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
22 # CHECK-V7A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
28 # CHECK-V7A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
30 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
31 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
32 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
33 # CHECK-V8A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
39 # CHECK-V8A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
[all …]
Dthumb-vmrs_vmsr.txt27 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
28 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
29 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
30 # CHECK-V7A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
38 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
39 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
40 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
41 # CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
49 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
50 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dvmrs_vmsr.s22 vmrs APSR_nzcv, fpscr
23 vmrs apsr_nzcv, fpscr
25 vmrs r10, fpscr
31 vmrs sp, fpscr
32 vmrs pc, fpscr
118 vmsr fpscr, APSR_nzcv
119 vmsr fpscr, r0
122 vmsr fpscr, r10
123 vmsr fpscr, sp
124 vmsr fpscr, pc
Dsimple-fp-encoding.s132 vmrs APSR_nzcv, fpscr
133 vmrs apsr_nzcv, fpscr
140 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
141 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
142 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
166 @ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
167 vmrs r0, fpscr
177 @ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
178 vmsr fpscr, r0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfpscr-intrinsics.ll9 ; CHECK: vmrs r{{[0-9]+}}, fpscr
25 ; CHECK: vmrs r{{[0-9]+}}, fpscr
26 %0 = tail call i32 @llvm.arm.get.fpscr()
28 ; CHECK: vmsr fpscr, r{{[0-9]+}}
29 tail call void @llvm.arm.set.fpscr(i32 1)
30 ; CHECK: vmrs r{{[0-9]+}}, fpscr
31 %1 = tail call i32 @llvm.arm.get.fpscr()
38 declare i32 @llvm.arm.get.fpscr()
41 declare void @llvm.arm.set.fpscr(i32)
Dinlineasm-X-constraint.ll10 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
15 ; CHECK: vmsr fpscr
22 …call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwi…
29 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
34 ; CHECK: vmsr fpscr
40 call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind
48 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
57 ; unsigned int fpscr;
58 ; asm volatile ("vmsr fpscr,%1" : "=X" ((vector_res_int8x8)) : "r" (fpscr));
63 ; CHECK: vmsr fpscr
[all …]
Dfp16-instructions.ll216 ; CHECK-SOFTFP-FP16: vmrs APSR_nzcv, fpscr
219 ; CHECK-SOFTFP-FULLFP16: vmrs APSR_nzcv, fpscr
712 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
716 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
720 ; CHECK-SOFTFP-FP16-T32: vmrs APSR_nzcv, fpscr
738 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
742 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
746 ; CHECK-SOFTFP-FP16-T32-NEXT: vmrs APSR_nzcv, fpscr
759 ; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
763 ; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
[all …]
Dspecial-reg.ll31 ; ARM: vmrs r0, fpscr
64 ; ARM: vmsr fpscr, r0
77 !3 = !{!"fpscr"}
Dfloat-helpers.s147 ; CHECK-SOFTFP-NEXT: vmrs APSR_nzcv, fpscr
154 ; CHECK-HARDFP-SP-NEXT: vmrs APSR_nzcv, fpscr
178 ; CHECK-SOFTFP-NEXT: vmrs APSR_nzcv, fpscr
185 ; CHECK-HARDFP-SP-NEXT: vmrs APSR_nzcv, fpscr
209 ; CHECK-SOFTFP-NEXT: vmrs APSR_nzcv, fpscr
216 ; CHECK-HARDFP-SP-NEXT: vmrs APSR_nzcv, fpscr
240 ; CHECK-SOFTFP-NEXT: vmrs APSR_nzcv, fpscr
247 ; CHECK-HARDFP-SP-NEXT: vmrs APSR_nzcv, fpscr
271 ; CHECK-SOFTFP-NEXT: vmrs APSR_nzcv, fpscr
278 ; CHECK-HARDFP-SP-NEXT: vmrs APSR_nzcv, fpscr
[all …]
Difcvt11.ll21 ; CHECK: vmrs APSR_nzcv, fpscr
36 ; CHECK: vmrs APSR_nzcv, fpscr
/external/llvm/test/CodeGen/ARM/
Dinlineasm-X-constraint.ll10 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
15 ; CHECK: vmsr fpscr
22 …call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwi…
29 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
34 ; CHECK: vmsr fpscr
40 call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind
48 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
57 ; unsigned int fpscr;
58 ; asm volatile ("vmsr fpscr,%1" : "=X" ((vector_res_int8x8)) : "r" (fpscr));
63 ; CHECK: vmsr fpscr
[all …]
Dspecial-reg.ll31 ; ARM: vmrs r0, fpscr
64 ; ARM: vmsr fpscr, r0
77 !3 = !{!"fpscr"}
Difcvt11.ll21 ; CHECK: vmrs APSR_nzcv, fpscr
36 ; CHECK: vmrs APSR_nzcv, fpscr
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dsimple-fp-encoding.s117 @ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
118 @ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
119 vmrs apsr_nzcv, fpscr
130 @ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
131 vmrs r0, fpscr
137 @ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
138 vmsr fpscr, r0
/external/capstone/suite/MC/ARM/
Dsimple-fp-encoding.s.cs44 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr
45 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr
46 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr
58 0x10,0x0a,0xf1,0xee = vmrs r0, fpscr
63 0x10,0x0a,0xe1,0xee = vmsr fpscr, r0
/external/llvm/test/MC/ARM/
Dsimple-fp-encoding.s120 vmrs APSR_nzcv, fpscr
121 vmrs apsr_nzcv, fpscr
128 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
129 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
130 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
154 @ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
155 vmrs r0, fpscr
165 @ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
166 vmsr fpscr, r0
/external/vixl/test/aarch32/
Dtest-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc140 uint32_t fpscr; member
1442 __ Ldr(fpsr_bits, MemOperand(input_ptr, offsetof(Inputs, fpscr))); in TestHelper()
1455 __ Str(fpsr_bits, MemOperand(result_ptr, offsetof(Inputs, fpscr))); in TestHelper()
1481 printf("0x%08" PRIx32, results[i]->outputs[j].fpscr); in TestHelper()
1508 uint32_t fpscr = results[i]->outputs[j].fpscr; in TestHelper() local
1512 uint32_t fpscr_input = kTests[i].inputs[j].fpscr; in TestHelper()
1516 uint32_t fpscr_ref = reference[i].outputs[j].fpscr; in TestHelper()
1521 if (((fpscr != fpscr_ref) || (rd != rd_ref) || (rn != rn_ref) || in TestHelper()
1551 printf("0x%08" PRIx32, fpscr); in TestHelper()
Dtest-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc140 uint32_t fpscr; member
1442 __ Ldr(fpsr_bits, MemOperand(input_ptr, offsetof(Inputs, fpscr))); in TestHelper()
1455 __ Str(fpsr_bits, MemOperand(result_ptr, offsetof(Inputs, fpscr))); in TestHelper()
1481 printf("0x%08" PRIx32, results[i]->outputs[j].fpscr); in TestHelper()
1508 uint32_t fpscr = results[i]->outputs[j].fpscr; in TestHelper() local
1512 uint32_t fpscr_input = kTests[i].inputs[j].fpscr; in TestHelper()
1516 uint32_t fpscr_ref = reference[i].outputs[j].fpscr; in TestHelper()
1521 if (((fpscr != fpscr_ref) || (rd != rd_ref) || (rn != rn_ref) || in TestHelper()
1551 printf("0x%08" PRIx32, fpscr); in TestHelper()
/external/compiler-rt/test/sanitizer_common/TestCases/Linux/
Dptrace.cc70 unsigned fpscr = *(unsigned*)(regbuf + (32 * 8)); in main() local
71 printf ("%x\n", fpscr); in main()
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Difcvt11.ll21 ; CHECK: vmrs apsr_nzcv, fpscr
36 ; CHECK: vmrs apsr_nzcv, fpscr
/external/compiler-rt/lib/builtins/arm/
Dgtsf2vfp.S25 vmrs apsr_nzcv, fpscr
Dgesf2vfp.S25 vmrs apsr_nzcv, fpscr
Dunordsf2vfp.S25 vmrs apsr_nzcv, fpscr
Dlesf2vfp.S25 vmrs apsr_nzcv, fpscr
Dltsf2vfp.S25 vmrs apsr_nzcv, fpscr

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