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Searched refs:frsp (Results 1 – 23 of 23) sorted by relevance

/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-fp.s.cs75 0xfc,0x40,0x18,0x18 = frsp 2, 3
76 0xfc,0x40,0x18,0x19 = frsp. 2, 3
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s245 # CHECK-BE: frsp 2, 3 # encoding: [0xfc,0x40,0x18,0x18]
246 # CHECK-LE: frsp 2, 3 # encoding: [0x18,0x18,0x40,0xfc]
247 frsp 2, 3
248 # CHECK-BE: frsp. 2, 3 # encoding: [0xfc,0x40,0x18,0x19]
249 # CHECK-LE: frsp. 2, 3 # encoding: [0x19,0x18,0x40,0xfc]
250 frsp. 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s251 # CHECK-BE: frsp 2, 3 # encoding: [0xfc,0x40,0x18,0x18]
252 # CHECK-LE: frsp 2, 3 # encoding: [0x18,0x18,0x40,0xfc]
253 frsp 2, 3
254 # CHECK-BE: frsp. 2, 3 # encoding: [0xfc,0x40,0x18,0x19]
255 # CHECK-LE: frsp. 2, 3 # encoding: [0x19,0x18,0x40,0xfc]
256 frsp. 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfast-isel-conversion.ll27 ; PPC970: frsp
45 ; PPC970: frsp
65 ; PPC970: frsp
86 ; PPC970: frsp
218 ; PPC970: frsp
239 ; PPC970: frsp
Di32-to-float.ll18 ; CHECK: frsp 1, [[REG3]]
25 ; CHECK-PWR6: frsp 1, [[REG2]]
Dfp-to-int-to-fp.ll20 ; PPC64: frsp 1, [[REG2]]
Drecipest.ll84 ; CHECK-NEXT: frsp
Dbuild-vector-tests.ll3 ; RUN: -check-prefix=P9BE -implicit-check-not frsp
6 ; RUN: -check-prefix=P9LE -implicit-check-not frsp
9 ; RUN: -check-prefix=P8BE -implicit-check-not frsp
12 ; RUN: -check-prefix=P8LE -implicit-check-not frsp
/external/llvm/test/CodeGen/PowerPC/
Dfast-isel-conversion.ll30 ; PPC970: frsp
55 ; PPC970: frsp
79 ; PPC970: frsp
103 ; PPC970: frsp
260 ; PPC970: frsp
284 ; PPC970: frsp
Di32-to-float.ll18 ; CHECK: frsp 1, [[REG3]]
25 ; CHECK-PWR6: frsp 1, [[REG2]]
Dfp-to-int-to-fp.ll21 ; PPC64: frsp 1, [[REG2]]
Drecipest.ll77 ; CHECK-NEXT: frsp
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-fp.txt222 # CHECK: frsp 2, 3
225 # CHECK: frsp. 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-fp.txt222 # CHECK: frsp 2, 3
225 # CHECK: frsp. 2, 3
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCSchedule.td195 // frsp FPGeneral
DREADME.txt516 frsp f1, f0
DPPCInstrInfo.td993 "frsp $frD, $frB", FPGeneral,
/external/v8/src/compiler/ppc/
Dcode-generator-ppc.cc293 __ frsp(i.OutputDoubleRegister(), i.OutputDoubleRegister()); \
302 __ frsp(i.OutputDoubleRegister(), i.OutputDoubleRegister()); \
1870 ASSEMBLE_FLOAT_UNOP_RC(frsp, 0); in AssembleArchInstruction()
/external/v8/src/ppc/
Dassembler-ppc.h1223 void frsp(const DoubleRegister frt, const DoubleRegister frb,
Dconstants-ppc.h1517 V(frsp, FRSP, 0xFC000018) \
Dassembler-ppc.cc1827 void Assembler::frsp(const DoubleRegister frt, const DoubleRegister frb, in frsp() function in v8::internal::Assembler
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td2112 "frsp", "$frD, $frB", IIC_FPGeneral,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td2346 "frsp", "$frD, $frB", IIC_FPGeneral,