Searched refs:fuses (Results 1 – 25 of 29) sorted by relevance
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| /external/u-boot/doc/ |
| D | README.imx6 | 17 For reading the MAC address fuses on a MX6Q:
29 Base address for the fuses: 0x400
33 As the fuses are arranged in banks of 8 words:
50 Base address for the fuses: 0x400
54 As the fuses are arranged in banks of 8 words:
77 Rev. 1, 04/2013" document. For example, for the MAC fuses we have:
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| D | README.fuse | 13 A fuse word is the smallest group of fuses that can be read at once from the
36 This is useful to know the true value of fuses if an override has been
61 fuses have already been programmed or are locked (if the SoC allows to
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| D | README.fsl_iim | 18 Some fuse bit or word slots may not have the corresponding fuses actually
22 conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
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| D | README.mxc_ocotp | 21 Some fuse bit or word slots may not have the corresponding fuses actually
25 conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
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| D | README.imx5 | 36 After programming a MAC address, consider locking the MAC fuses. This is
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| D | README.mxs | 258 user changes STRIDE by blowing fuses, the user also has to change
260 blowing fuses, the user also has to change "update_nand_count"
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| D | README.imximage | 101 if the fuses for the keys are burned.
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| D | README.armada-secureboot | 292 If the SEC_FUSE_DUMP option was not set, the commands needed to burn the fuses
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| /external/u-boot/drivers/misc/ |
| D | rockchip-efuse.c | 56 u8 fuses[128]; in dump_efuses() local
67 ret = misc_read(dev, 0, &fuses, sizeof(fuses)); in dump_efuses()
74 print_buffer(0, fuses, 1, 128, 16); in dump_efuses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64.td | 145 "CPU fuses arithmetic+bcc operations">;
149 "CPU fuses arithmetic + cbz/cbnz operations">;
153 "CPU fuses address generation and memory operations">;
157 "CPU fuses AES crypto operations">;
161 "CPU fuses conditional select operations">;
165 "CPU fuses literal generation operations">;
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| /external/u-boot/arch/arm/mach-imx/ |
| D | Kconfig | 75 bool "Read NXP board revision from fuses"
79 stored in the fuses. Select this option if you want to be able to
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| /external/u-boot/board/toradex/colibri_imx6/ |
| D | Kconfig | 38 pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
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| /external/u-boot/board/toradex/apalis_imx6/ |
| D | Kconfig | 38 pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
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| /external/tensorflow/tensorflow/core/api_def/base_api/ |
| D | api_def_ExperimentalMapAndBatchDataset.pbtxt | 46 summary: "Creates a dataset that fuses mapping with batching."
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| D | api_def_ExperimentalNumaMapAndBatchDataset.pbtxt | 46 summary: "Creates a dataset that fuses mapping with batching."
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | machine-combiner-madd.ll | 12 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
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| /external/u-boot/board/boundary/nitrogen6x/ |
| D | README.mx6qsabrelite | 35 from the fuses.
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| /external/u-boot/arch/arm/dts/ |
| D | tegra30.dtsi | 826 nvidia.xcvr-setup-use-fuses;
863 nvidia.xcvr-setup-use-fuses;
899 nvidia.xcvr-setup-use-fuses;
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| /external/u-boot/drivers/nvme/ |
| D | nvme.h | 65 __le16 fuses; member
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARM.td | 142 "CPU fuses AES crypto operations">;
146 "CPU fuses literal generation operations">;
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| /external/tensorflow/tensorflow/lite/g3doc/guide/ |
| D | ops_custom.md | 182 TensorFlow. If you are defining a new operator that fuses many operators or you
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| /external/u-boot/cmd/ |
| D | Kconfig | 750 This allows reading, sensing, programming or overriding fuses
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSubtargetInfo.inc | 106 …{ "arith-bcc-fusion", "CPU fuses arithmetic+bcc operations", { AArch64::FeatureArithmeticBccFusion…
107 …{ "arith-cbz-fusion", "CPU fuses arithmetic + cbz/cbnz operations", { AArch64::FeatureArithmeticCb…
122 …{ "fuse-address", "CPU fuses address generation and memory operations", { AArch64::FeatureFuseAddr…
123 { "fuse-aes", "CPU fuses AES crypto operations", { AArch64::FeatureFuseAES }, { } },
124 { "fuse-csel", "CPU fuses conditional select operations", { AArch64::FeatureFuseCCSelect }, { } },
125 …{ "fuse-literals", "CPU fuses literal generation operations", { AArch64::FeatureFuseLiterals }, { …
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSubtargetInfo.inc | 247 { "fuse-aes", "CPU fuses AES crypto operations", { ARM::FeatureFuseAES }, { } },
248 { "fuse-literals", "CPU fuses literal generation operations", { ARM::FeatureFuseLiterals }, { } },
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| /external/jline/src/src/test/resources/jline/example/ |
| D | english.gz | |
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