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Searched refs:getCondCode (Results 1 – 25 of 26) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp687 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in SoftenSetCCOperands()
690 NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); in SoftenSetCCOperands()
726 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
769 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
787 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
906 DAG.getCondCode(ISD::SETEQ)); in ExpandFloatRes_FABS()
1231 Lo, Hi, DAG.getCondCode(ISD::SETLT)); in ExpandFloatRes_XINT_TO_FP()
1337 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1396 DAG.getCondCode(ISD::SETGE)); in ExpandFloatOp_FP_TO_UINT()
1419 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
[all …]
DLegalizeIntegerTypes.cpp2538 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2582 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2601 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2618 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
DLegalizeDAG.cpp3748 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3786 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3804 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
DSelectionDAG.cpp1217 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp888 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
898 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
979 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
985 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1013 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1021 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1053 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1079 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
DSIISelLowering.cpp5005 Op.getOperand(2), DAG.getCondCode(CCOpcode)); in LowerINTRINSIC_WO_CHAIN()
5020 Op.getOperand(2), DAG.getCondCode(CCOpcode)); in LowerINTRINSIC_WO_CHAIN()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h438 SDValue getCondCode(ISD::CondCode Cond);
571 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
580 LHS, RHS, True, False, getCondCode(Cond));
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1064 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1147 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
1153 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1181 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1189 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1221 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1247 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp881 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
934 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
956 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1578 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1674 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1691 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
DLegalizeIntegerTypes.cpp2866 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2920 LHSHi, RHSHi, LowCmp.getValue(1), DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2951 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2970 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2987 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
DLegalizeDAG.cpp1583 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1634 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3538 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3652 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3683 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
DTargetLowering.cpp267 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
273 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
DSelectionDAG.cpp1455 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp896 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
988 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1010 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1632 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1691 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1708 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
DLegalizeIntegerTypes.cpp3025 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
3081 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
3110 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
3129 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
3146 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
DLegalizeDAG.cpp1604 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1616 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3722 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3836 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3867 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
DTargetLowering.cpp272 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
278 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
DSelectionDAG.cpp1541 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h625 SDValue getCondCode(ISD::CondCode Cond);
821 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
842 LHS, RHS, True, False, getCondCode(Cond));
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DSelectionDAG.h717 SDValue getCondCode(ISD::CondCode Cond);
959 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
980 LHS, RHS, True, False, getCondCode(Cond));
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp450 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon92cf716e0311::ARMOperand
928 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
929 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
955 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addITCondCodeOperands()
1676 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp354 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon26fd99540211::AArch64Operand
1279 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
1800 OS << "<condcode " << getCondCode() << ">"; in print()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp496 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anonf77cce8c0111::AArch64Operand
1547 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
1995 OS << "<condcode " << getCondCode() << ">"; in print()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp603 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonef5d38c20311::ARMOperand
1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1762 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
1788 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2883 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
4797 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp840 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon7876b5fa0111::ARMOperand
2014 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2015 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2041 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
3208 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
5008 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()

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