| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); in printInst()
115 MI->getOperand(3).getImm() == -4) { in printInst()
136 MI->getOperand(4).getImm() == 4) { in printInst()
206 O << '#' << Op.getImm(); in printOperand()
230 O << "[pc, #" << MO1.getImm() << "]"; in printT2LdrLabelOperand()
249 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
114 .addImm(MI->getOperand(0).getImm()) in EmitInstruction()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 78 .getImm(); in getCFAluSize()
85 .getImm(); in isCFAluEnabled()
126 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
127 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
128 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
129 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
130 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
142 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
143 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 89 .getImm(); in getCFAluSize()
96 .getImm(); in isCFAluEnabled()
137 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
138 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
139 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
140 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
141 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
142 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
153 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
154 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
114 .addImm(MI->getOperand(0).getImm()) in EmitInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 93 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
104 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
115 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
124 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
130 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
153 MI->getOperand(3).getImm() == -4) { in printInst()
182 MI->getOperand(4).getImm() == 4) { in printInst()
291 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand()
335 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
364 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
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|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 85 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
96 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
122 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
145 MI->getOperand(3).getImm() == -4) { in printInst()
174 MI->getOperand(4).getImm() == 4) { in printInst()
279 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand()
323 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
352 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
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|
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 36 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
41 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
46 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmOperand()
51 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
56 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
61 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
66 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
71 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
93 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset()
101 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 47 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
49 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
50 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
54 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
59 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
64 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
153 OS << formatHex(Op.getImm()); in printOperand()
164 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
178 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
190 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
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|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 60 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
61 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
62 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
93 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
94 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
116 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
148 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
244 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
251 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU2ImmOperand()
258 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU3ImmOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 72 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
73 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
74 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
106 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
107 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
129 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
153 unsigned char L = MI->getOperand(0).getImm(); in printInst()
180 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
276 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
285 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 118 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
141 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
148 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
199 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
204 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
207 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
208 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
209 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
211 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 116 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
139 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
197 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
202 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
205 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
206 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
207 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
209 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
[all …]
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| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 47 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
49 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
50 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
54 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
59 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
64 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
153 OS << formatHex(Op.getImm()); in printOperand()
164 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
178 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
190 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 208 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
219 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
240 return MO.getImm(); in getAdrLabelOpValue()
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
302 return MO.getImm(); in getCondBranchTargetOpValue()
324 return MO.getImm(); in getLoadLiteralOpValue()
340 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getMemExtendOpValue()
341 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm(); in getMemExtendOpValue()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
45 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
53 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
62 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
67 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
72 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
77 O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm())); in printS13ImmDecOperand()
83 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
88 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
110 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 167 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
239 unsigned SoImm = MI.getOperand(Op).getImm(); in getSOImmOpValue()
255 unsigned SoImm = MI.getOperand(Op).getImm(); in getT2SOImmOpValue()
280 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
419 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
438 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
465 if (MO.isImm()) return MO.getImm(); in getBranchTargetOpValue()
502 return encodeThumbBLOffset(MO.getImm()); in getThumbBLTargetOpValue()
514 return encodeThumbBLOffset(MO.getImm()); in getThumbBLXTargetOpValue()
525 return (MO.getImm() >> 1); in getThumbBRTargetOpValue()
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 193 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
204 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
225 return MO.getImm(); in getAdrLabelOpValue()
250 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
252 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
256 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12)); in getAddSubImmOpValue()
278 return MO.getImm(); in getCondBranchTargetOpValue()
300 return MO.getImm(); in getLoadLiteralOpValue()
316 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getMemExtendOpValue()
317 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm(); in getMemExtendOpValue()
[all …]
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
77 switch (Op3.getImm()) { in printInst()
113 int64_t immr = Op2.getImm(); in printInst()
114 int64_t imms = Op3.getImm(); in printInst()
144 if (Op2.getImm() > Op3.getImm()) { in printInst()
147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
163 int ImmR = MI->getOperand(3).getImm(); in printInst()
164 int ImmS = MI->getOperand(4).getImm(); in printInst()
230 int Shift = MI->getOperand(2).getImm(); in printInst()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 38 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
39 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
40 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
71 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
72 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
94 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
119 char Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand()
126 unsigned char Value = MI->getOperand(OpNo).getImm(); in printU5ImmOperand()
133 unsigned char Value = MI->getOperand(OpNo).getImm(); in printU6ImmOperand()
140 O << (short)MI->getOperand(OpNo).getImm(); in printS16ImmOperand()
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 144 const MCExpr *getImm() const { in getImm() function
392 addExpr(Inst, getImm()); in addImmOperands()
397 addExpr(Inst, getImm()); in addBrTargetOperands()
402 addExpr(Inst, getImm()); in addCallTargetOperands()
407 addExpr(Inst, getImm()); in addCondCodeOperands()
441 addExpr(Inst, getImm()); in addImmShiftOperands()
446 addExpr(Inst, getImm()); in addImm10Operands()
451 if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(getImm())) in addLoImm16Operands()
454 else if (isa<LanaiMCExpr>(getImm())) { in addLoImm16Operands()
456 const LanaiMCExpr *SymbolRefExpr = dyn_cast<LanaiMCExpr>(getImm()); in addLoImm16Operands()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 159 const MCExpr *getImm() const { in getImm() function
407 addExpr(Inst, getImm()); in addImmOperands()
412 addExpr(Inst, getImm()); in addBrTargetOperands()
417 addExpr(Inst, getImm()); in addCallTargetOperands()
422 addExpr(Inst, getImm()); in addCondCodeOperands()
456 addExpr(Inst, getImm()); in addImmShiftOperands()
461 addExpr(Inst, getImm()); in addImm10Operands()
466 if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(getImm())) in addLoImm16Operands()
469 else if (isa<LanaiMCExpr>(getImm())) { in addLoImm16Operands()
471 const LanaiMCExpr *SymbolRefExpr = dyn_cast<LanaiMCExpr>(getImm()); in addLoImm16Operands()
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| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 98 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction()
107 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction()
110 MI.getOperand(2).getImm(), in encodeInstruction()
111 MI.getOperand(3).getImm(), in encodeInstruction()
112 MI.getOperand(4).getImm(), in encodeInstruction()
113 MI.getOperand(5).getImm() in encodeInstruction()
116 MI.getOperand(6).getImm() & 0x1F, in encodeInstruction()
117 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction()
118 MI.getOperand(8).getImm() & 0x1F in encodeInstruction()
178 return MO.getImm(); in getMachineOpValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 114 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction()
123 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction()
126 MI.getOperand(2).getImm(), in encodeInstruction()
127 MI.getOperand(3).getImm(), in encodeInstruction()
128 MI.getOperand(4).getImm(), in encodeInstruction()
129 MI.getOperand(5).getImm() in encodeInstruction()
132 MI.getOperand(6).getImm() & 0x1F, in encodeInstruction()
133 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction()
134 MI.getOperand(8).getImm() & 0x1F in encodeInstruction()
194 return MO.getImm(); in getMachineOpValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 207 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
307 unsigned SoImm = MO.getImm(); in getSOImmOpValue()
335 return MO.getImm(); in getModImmOpValue()
352 unsigned SoImm = MO.getImm(); in getT2SOImmOpValue()
382 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
551 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
570 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
598 if (MO.isImm()) return MO.getImm(); in getBranchTargetOpValue()
636 return encodeThumbBLOffset(MO.getImm()); in getThumbBLTargetOpValue()
649 return encodeThumbBLOffset(MO.getImm()); in getThumbBLXTargetOpValue()
[all …]
|