Searched refs:getLdStRegOp (Results 1 – 2 of 2) sorted by relevance
584 static const MachineOperand &getLdStRegOp(const MachineInstr &MI, in getLdStRegOp() function627 getLdStRegOp(MI).getReg() == AArch64::WZR; in isPromotableZeroStoreInst()686 .addOperand(getLdStRegOp(*RtNewDest)) in mergeNarrowInsns()711 .addOperand(getLdStRegOp(*Rt2MI)) in mergeNarrowInsns()712 .addReg(getLdStRegOp(*RtNewDest).getReg()) in mergeNarrowInsns()719 .addOperand(getLdStRegOp(*RtMI)) in mergeNarrowInsns()720 .addReg(getLdStRegOp(*RtNewDest).getReg()) in mergeNarrowInsns()725 .addOperand(getLdStRegOp(*RtMI)) in mergeNarrowInsns()726 .addReg(getLdStRegOp(*RtNewDest).getReg()) in mergeNarrowInsns()735 .addOperand(getLdStRegOp(*RtMI)) in mergeNarrowInsns()[all …]
544 static const MachineOperand &getLdStRegOp(const MachineInstr &MI, in getLdStRegOp() function581 getLdStRegOp(MI).getReg() == AArch64::WZR; in isPromotableZeroStoreInst()796 MachineOperand RegOp0 = getLdStRegOp(*RtMI); in mergePairedInsns()797 MachineOperand RegOp1 = getLdStRegOp(*Rt2MI); in mergePairedInsns()812 unsigned Reg = getLdStRegOp(*I).getReg(); in mergePairedInsns()886 unsigned LdRt = getLdStRegOp(*LoadI).getReg(); in promoteLoadFromStore()887 const MachineOperand &StMO = getLdStRegOp(*StoreI); in promoteLoadFromStore()888 unsigned StRt = getLdStRegOp(*StoreI).getReg(); in promoteLoadFromStore()1077 ModifiedRegUnits.available(getLdStRegOp(MI).getReg())) { in findMatchingStore()1162 unsigned Reg = getLdStRegOp(FirstMI).getReg(); in findMatchingInsn()[all …]