| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 107 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
108 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
753 bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth( in getMemOpBaseRegImmOfsWidth() function in LanaiInstrInfo
806 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); in getMemOpBaseRegImmOfs()
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| D | LanaiInstrInfo.h | 75 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 108 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
109 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
750 bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth( in getMemOpBaseRegImmOfsWidth() function in LanaiInstrInfo
803 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); in getMemOpBaseRegImmOfs()
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| D | LanaiInstrInfo.h | 74 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 100 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
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| D | AArch64InstrInfo.cpp | 676 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
677 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
1568 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); in getMemOpBaseRegImmOfs()
1572 bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth( in getMemOpBaseRegImmOfsWidth() function in AArch64InstrInfo
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 117 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
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| D | AArch64InstrInfo.cpp | 1097 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
1098 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
2108 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); in getMemOpBaseRegImmOfs()
2111 bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth( in getMemOpBaseRegImmOfsWidth() function in AArch64InstrInfo
5334 if (!getMemOpBaseRegImmOfsWidth(MI, Base, Offset, DummyWidth, &RI) || in getOutliningType()
5371 !getMemOpBaseRegImmOfsWidth(MI, Base, Offset, Width, &RI) || in fixupPostOutline()
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