Home
last modified time | relevance | path

Searched refs:getNumAllocatableRegs (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/CodeGen/
DRegisterClassInfo.cpp136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
178 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC); in computePSetLimit()
DRegAllocGreedy.cpp767 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
768 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
1570 return RCI.getNumAllocatableRegs(ConstrainedRC); in getNumAllocatableRegsForConstraints()
1601 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
DMachineScheduler.cpp2579 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegisterClassInfo.cpp148 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
189 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC); in computePSetLimit()
DRegAllocGreedy.cpp910 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
911 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
2035 return RCI.getNumAllocatableRegs(ConstrainedRC); in getNumAllocatableRegsForConstraints()
2067 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
DMachineScheduler.cpp2661 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterClassInfo.h80 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() function
DRegisterClassInfo.cpp104 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
DRegisterCoalescer.cpp1087 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2; in shouldJoinPhys()
1106 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC); in isWinToJoinCrossClass()
1136 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); in isWinToJoinCrossClass()
1141 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC); in isWinToJoinCrossClass()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h90 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() function
/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DGCNSchedStrategy.cpp45 ->getNumAllocatableRegs(&AMDGPU::SGPR_32RegClass) - ErrorMargin; in initialize()
47 ->getNumAllocatableRegs(&AMDGPU::VGPR_32RegClass) - ErrorMargin; in initialize()