Searched refs:getRegClasses (Results 1 – 20 of 20) sorted by relevance
184 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()201 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()221 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()253 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
136 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()197 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()204 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()990 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()1143 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()1179 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()1590 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump()1609 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { in debugDump()
696 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function698 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
298 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()313 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
931 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()988 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()1532 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()1817 auto &RegClasses = getRegClasses(); in computeRegUnitSets()2271 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()
30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
1213 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
60 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses(); in runEnums()333 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); in runMCDesc()448 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()496 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()
273 ArrayRef<CodeGenRegisterClass*> getRegClasses() const { in getRegClasses() function
187 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses(); in getRegisterVTs()204 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses(); in ReadLegalValueTypes()
464 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses(); in computeSubClasses()808 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses(); in getRegClassForRegister()
29 ArrayRef<CodeGenRegisterClass*> RCs = T.getRegBank().getRegClasses(); in getRegisterValueType()
707 Target.getRegBank().getRegClasses(); in EmitRegIsInRegClass()
918 Target.getRegBank().getRegClasses(); in BuildRegisterClasses()
122 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()192 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()199 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()981 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()1138 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()1174 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()
649 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function651 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
246 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()261 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
851 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()1334 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()1614 auto &RegClasses = getRegClasses(); in computeRegUnitSets()2065 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()
1204 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()