Searched refs:getSignExtendVectorInReg (Results 1 – 8 of 8) sorted by relevance
/external/llvm/include/llvm/CodeGen/ |
D | SelectionDAG.h | 703 SDValue getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorTypes.cpp | 2579 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT); in WidenVecRes_Convert() 2659 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT); in WidenVecRes_EXTEND_VECTOR_INREG() 3508 return DAG.getSignExtendVectorInReg(InOp, DL, VT); in WidenVecOp_EXTEND()
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D | SelectionDAG.cpp | 1132 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, in getSignExtendVectorInReg() function in SelectionDAG
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D | DAGCombiner.cpp | 9253 return DAG.getSignExtendVectorInReg(N0.getOperand(0), SDLoc(N), VT); in visitSIGN_EXTEND_INREG()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | SelectionDAG.h | 797 SDValue getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorTypes.cpp | 2442 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT); in WidenVecRes_EXTEND_VECTOR_INREG() 3179 return DAG.getSignExtendVectorInReg(InOp, DL, VT); in WidenVecOp_EXTEND()
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D | SelectionDAG.cpp | 1051 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, in getSignExtendVectorInReg() function in SelectionDAG
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 5417 return X86ISD::VSEXT == Opc ? DAG.getSignExtendVectorInReg(In, DL, VT) in getExtendInVec() 19370 OpLo = DAG.getSignExtendVectorInReg(OpLo, dl, HalfVT); in LowerSIGN_EXTEND() 19371 OpHi = DAG.getSignExtendVectorInReg(OpHi, dl, HalfVT); in LowerSIGN_EXTEND() 19595 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT); in LowerLoad() 37748 ? DAG.getSignExtendVectorInReg(ExOp, DL, VT) in combineToExtendVectorInReg() 37764 ? DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT) in combineToExtendVectorInReg()
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