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Searched refs:getValueAsListOfDefs (Results 1 – 25 of 49) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenSchedule.cpp291 if (!ModelKey->getValueAsListOfDefs("IID").empty()) in addProcModel()
307 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
313 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
316 RecVec Selected = Variant->getValueAsListOfDefs("Selected"); in scanSchedRW()
338 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
352 RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
366 RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
411 findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence, in collectSchedRW()
472 RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites"); in hasReadOfWrite()
614 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
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DPredicateExpander.cpp234 return expandCheckPseudo(OS, Rec->getValueAsListOfDefs("ValidOpcodes")); in expandPredicate()
237 return expandCheckOpcode(OS, Rec->getValueAsListOfDefs("ValidOpcodes")); in expandPredicate()
240 return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"), in expandPredicate()
244 return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"), in expandPredicate()
DSubtargetEmitter.cpp206 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
241 RecVec FeatureList = Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
273 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
286 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
333 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
364 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
378 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
603 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResourceSubUnits()
799 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
949 SubResources = PRDef->getValueAsListOfDefs("Resources"); in ExpandProcResources()
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DCodeGenHwModes.cpp33 std::vector<Record*> Modes = R->getValueAsListOfDefs("Modes"); in HwModeSelect()
34 std::vector<Record*> Objects = R->getValueAsListOfDefs("Objects"); in HwModeSelect()
DDFAPacketizerEmitter.cpp664 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU"); in collectAllFuncUnits()
705 std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD"); in collectAllComboFuncs()
717 FuncData->getValueAsListOfDefs("FuncList"); in collectAllComboFuncs()
749 ItinData->getValueAsListOfDefs("Stages"); in collectOneInsnClass()
765 Stage->getValueAsListOfDefs("Units"); in collectOneInsnClass()
884 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID"); in run()
DCodeGenTarget.cpp235 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); in getAsmParser()
247 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariant()
259 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariantCount()
266 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); in getAsmWriter()
459 RootNodes = R->getValueAsListOfDefs("RootNodes"); in ComplexPattern()
474 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); in ComplexPattern()
DInstrInfoEmitter.cpp447 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); in run()
452 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); in run()
624 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); in emitRecord()
630 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); in emitRecord()
DSDNodeProperties.cpp18 for (Record *Property : R->getValueAsListOfDefs("Properties")) { in parseSDPatternOperatorProperties()
DCodeGenSchedule.h251 return !ItinsDef->getValueAsListOfDefs("IID").empty(); in hasItineraries()
332 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) { in getModelOrItinDef()
DInstrDocsEmitter.cpp218 II->TheDef->getValueAsListOfDefs("Predicates"); in EmitInstrDocs()
DCodeGenRegisters.cpp80 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); in updateComponents()
93 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); in updateComponents()
169 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); in buildObjectGraph()
170 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs"); in buildObjectGraph()
191 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases"); in buildObjectGraph()
619 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); in expand()
738 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); in CodeGenRegisterClass()
DRegisterBankEmitter.cpp67 for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses")) in getExplictlySpecifiedRegisterClasses()
/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp170 if (!ModelKey->getValueAsListOfDefs("IID").empty()) in addProcModel()
186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
192 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
195 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected"); in scanSchedRW()
217 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
231 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
246 RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
293 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence, in collectSchedRW()
358 RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites"); in hasReadOfWrite()
511 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
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DSubtargetEmitter.cpp193 Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
239 Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
279 ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
292 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
340 ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
372 std::vector<Record*> FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
386 std::vector<Record*> BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
617 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
762 SubResources = PRDef->getValueAsListOfDefs("Resources"); in ExpandProcResources()
783 RecVec SuperResources = PR->getValueAsListOfDefs("Resources"); in ExpandProcResources()
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DCodeGenTarget.cpp183 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); in getAsmParser()
195 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariant()
207 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); in getAsmParserVariantCount()
214 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); in getAsmWriter()
394 RootNodes = R->getValueAsListOfDefs("RootNodes"); in ComplexPattern()
398 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); in ComplexPattern()
DDFAPacketizerEmitter.cpp656 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU"); in collectAllFuncUnits()
698 std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD"); in collectAllComboFuncs()
711 FuncData->getValueAsListOfDefs("FuncList"); in collectAllComboFuncs()
743 ItinData->getValueAsListOfDefs("Stages"); in collectOneInsnClass()
759 Stage->getValueAsListOfDefs("Units"); in collectOneInsnClass()
878 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID"); in run()
DInstrInfoEmitter.cpp361 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); in run()
366 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); in run()
527 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); in emitRecord()
533 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); in emitRecord()
DCodeGenSchedule.h209 return !ItinsDef->getValueAsListOfDefs("IID").empty(); in hasItineraries()
284 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) { in getModelOrItinDef()
DCodeGenRegisters.cpp60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); in updateComponents()
73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); in updateComponents()
118 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); in buildObjectGraph()
119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs"); in buildObjectGraph()
140 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases"); in buildObjectGraph()
543 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); in expand()
665 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); in CodeGenRegisterClass()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DSubtargetEmitter.cpp105 Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
152 Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
216 ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
229 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
277 ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
311 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
325 std::vector<Record*> BPs = Proc->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
370 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID"); in EmitStageAndOperandCycleData()
DInstrInfoEmitter.cpp187 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); in run()
192 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); in run()
314 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); in emitRecord()
320 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); in emitRecord()
DCodeGenTarget.cpp146 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); in getAsmParser()
155 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); in getAsmWriter()
311 RootNodes = R->getValueAsListOfDefs("RootNodes"); in ComplexPattern()
315 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); in ComplexPattern()
DCodeGenRegisters.cpp55 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs"); in getSubRegs()
56 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); in getSubRegs()
147 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); in addSubRegsPreOrder()
165 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); in expand()
266 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); in CodeGenRegisterClass()
712 std::vector<Record*> RegList = Reg->TheDef->getValueAsListOfDefs("Aliases"); in computeOverlaps()
DCodeGenInstruction.cpp322 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
323 ImplicitUses = R->getValueAsListOfDefs("Uses"); in CodeGenInstruction()
/external/clang/utils/TableGen/
DClangAttrEmitter.cpp74 std::vector<Record *> Spellings = Attr.getValueAsListOfDefs("Spellings"); in GetFlattenedSpellings()
1410 std::vector<Record*> Accessors = R.getValueAsListOfDefs("Accessors"); in writeAttrAccessorDefinition()
1531 std::vector<Record *> Args = Attr->getValueAsListOfDefs("Args"); in emitClangAttrTypeArgList()
1587 std::vector<Record *> Args = Attr->getValueAsListOfDefs("Args"); in emitClangAttrIdentifierArgList()
1625 (void)R.getValueAsListOfDefs("Documentation"); in EmitClangAttrClass()
1641 std::vector<Record*> ArgRecords = R.getValueAsListOfDefs("Args"); in EmitClangAttrClass()
1819 std::vector<Record*> ArgRecords = R.getValueAsListOfDefs("Args"); in EmitClangAttrImpl()
2131 ArgRecords = R.getValueAsListOfDefs("Args"); in EmitClangAttrPCHRead()
2165 Args = R.getValueAsListOfDefs("Args"); in EmitClangAttrPCHWrite()
2254 std::vector<Record *> Spellings = Attr->getValueAsListOfDefs("Spellings"); in GenerateHasAttrSpellingStringSwitch()
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