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Searched refs:getZeroExtendInReg (Results 1 – 25 of 28) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp400 return DAG.getZeroExtendInReg(Res, dl, in PromoteIntRes_INT_EXTEND()
625 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); in PromoteIntRes_UADDSUBO()
958 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); in PromoteIntOp_MEMBARRIER()
1055 return DAG.getZeroExtendInReg(Op, dl, in PromoteIntOp_ZERO_EXTEND()
2383 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
DLegalizeTypes.h211 return DAG.getZeroExtendInReg(Op, dl, OldVT.getScalarType()); in ZExtPromotedInteger()
DLegalizeDAG.cpp1474 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); in LegalizeOp()
1549 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); in LegalizeOp()
2530 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); in ExpandLegalINT_TO_FP()
DDAGCombiner.cpp751 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); in ZExtPromoteOperand()
4216 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), in visitZERO_EXTEND()
4769 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); in visitSIGN_EXTEND_INREG()
7611 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); in SimplifySelectCC()
DTargetLowering.cpp1625 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); in SimplifyDemandedBits()
DSelectionDAG.cpp902 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT VT) { in getZeroExtendInReg() function in SelectionDAG
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp538 Value = DAG.getZeroExtendInReg(Value, dl, StVT); in LegalizeStoreOps()
927 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); in LegalizeLoadOps()
2380 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); in ExpandLegalINT_TO_FP()
2943 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
2947 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType); in ExpandNode()
2948 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
DLegalizeTypes.h281 return DAG.getZeroExtendInReg(Op, dl, OldVT.getScalarType()); in ZExtPromotedInteger()
DLegalizeIntegerTypes.cpp458 return DAG.getZeroExtendInReg(Res, dl, in PromoteIntRes_INT_EXTEND()
756 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); in PromoteIntRes_UADDSUBO()
1316 return DAG.getZeroExtendInReg(Op, dl, in PromoteIntOp_ZERO_EXTEND()
2863 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
DDAGCombiner.cpp1164 return DAG.getZeroExtendInReg(NewOp, DL, OldVT); in ZExtPromoteOperand()
8654 Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType()); in visitZERO_EXTEND()
8666 SDValue And = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType()); in visitZERO_EXTEND()
9267 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT.getScalarType()); in visitSIGN_EXTEND_INREG()
17949 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), in SimplifySelectCC()
DTargetLowering.cpp1028 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg( in SimplifyDemandedBits()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h467 SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT SrcTy);
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h230 return DAG.getZeroExtendInReg(Op, dl, OldVT.getScalarType()); in ZExtPromotedInteger()
DLegalizeIntegerTypes.cpp464 return DAG.getZeroExtendInReg(Res, dl, in PromoteIntRes_INT_EXTEND()
749 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); in PromoteIntRes_UADDSUBO()
1270 return DAG.getZeroExtendInReg(Op, dl, in PromoteIntOp_ZERO_EXTEND()
2702 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
DLegalizeDAG.cpp513 Value = DAG.getZeroExtendInReg(Value, dl, StVT); in LegalizeStoreOps()
900 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); in LegalizeLoadOps()
2346 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); in ExpandLegalINT_TO_FP()
2852 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType); in ExpandNode()
DDAGCombiner.cpp1021 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); in ZExtPromoteOperand()
6348 Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType()); in visitZERO_EXTEND()
6363 return DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType()); in visitZERO_EXTEND()
6977 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT); in visitSIGN_EXTEND_INREG()
14346 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), in SimplifySelectCC()
DTargetLowering.cpp923 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); in SimplifyDemandedBits()
DSelectionDAG.cpp1028 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg() function in SelectionDAG
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1197 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1427 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
DAMDGPUISelLowering.cpp3844 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1336 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1558 DAG.getZeroExtendInReg(Ret, DL, MemEltVT), in lowerPrivateExtLoad()
DAMDGPUISelLowering.cpp2678 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h691 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy);
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DSelectionDAG.h785 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp2221 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8); in buildVector32()
2375 ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy)); in extractVector()

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