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/external/llvm/test/CodeGen/Hexagon/
Dalu64.ll279 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
287 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
295 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
303 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
311 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
319 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
327 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
335 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
375 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
383 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dalu64.ll279 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
287 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
295 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
303 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
311 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
319 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
327 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
335 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
375 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
383 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll118 declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32)
120 %z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b)
125 declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32)
127 %z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b)
132 declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32)
134 %z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b)
139 declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32)
141 %z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b)
146 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
148 %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
[all …]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll118 declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32)
120 %z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b)
125 declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32)
127 %z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b)
132 declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32)
134 %z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b)
139 declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32)
141 %z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b)
146 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
148 %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-recip.s9 frecps h21, h16, h13
Dneon-scalar-by-elem-saturating-mla.s8 sqdmlal s11, h16, v8.h[4]
Dfullfp16-neon-neg.s282 frecps h21, h16, h13
/external/llvm/test/MC/AArch64/
Dneon-scalar-recip.s9 frecps h21, h16, h13
Dneon-scalar-by-elem-saturating-mla.s8 sqdmlal s11, h16, v8.h[4]
Dfullfp16-neon-neg.s282 frecps h21, h16, h13
/external/capstone/suite/MC/AArch64/
Dneon-scalar-by-elem-saturating-mla.s.cs4 0x0b,0x3a,0x48,0x5f = sqdmlal s11, h16, v8.h[4]
/external/llvm/unittests/Support/
DYAMLIOTest.cpp256 Hex16 h16; member
280 io.mapRequired("h16", bt.h16); in mapping()
330 EXPECT_EQ(map.h16, Hex16(0x8765)); in TEST()
357 map.h16 = 50000; in TEST()
386 EXPECT_EQ(map.h16, Hex16(50000)); in TEST()
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/Support/
DYAMLIOTest.cpp340 Hex16 h16; member
364 io.mapRequired("h16", bt.h16); in mapping()
414 EXPECT_EQ(map.h16, Hex16(0x8765)); in TEST()
441 map.h16 = 50000; in TEST()
470 EXPECT_EQ(map.h16, Hex16(50000)); in TEST()
/external/vixl/test/aarch64/
Dtest-api-aarch64.cc220 VIXL_CHECK(AreConsecutive(h16, h17, h18, h19)); in TEST()
Dtest-assembler-aarch64.cc10633 __ Fmov(h16, kFP16NegativeInfinity); in TEST()
10643 __ Fadd(h4, h16, h18); in TEST()
10644 __ Fadd(h5, h15, h16); in TEST()
10645 __ Fadd(h6, h16, h15); in TEST()
10771 __ Fmov(h16, kFP16NegativeInfinity); in TEST()
10780 __ Fsub(h4, h18, h16); in TEST()
10782 __ Fsub(h6, h16, h16); in TEST()
10909 __ Fmov(h16, kFP16NegativeInfinity); in TEST()
10919 __ Fmul(h4, h16, h20); in TEST()
10921 __ Fmul(h6, h19, h16); in TEST()
[all …]
Dtest-disasm-aarch64.cc2952 COMPARE(fccmp(h30, h16, NCFlag, pl), "fccmp h30, h16, #NzCv, pl"); in TEST()
2968 COMPARE(fccmpe(h30, h16, NCFlag, pl), "fccmpe h30, h16, #NzCv, pl"); in TEST()
7038 COMPARE_MACRO(Fminnmp(h16, v17.V2H()), "fminnmp h16, v17.2h"); in TEST()
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1246 hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.hh
1247 hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.hl
1248 hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.lh
1249 hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.ll
1250 hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.sat.hh
1251 hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.sat.hl
1252 hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.sat.lh
1253 hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.sat.ll
1297 hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.hh
1298 hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.hl
[all …]
DIntrinsicImpl.inc1272 "llvm.hexagon.A2.addh.h16.hh",
1273 "llvm.hexagon.A2.addh.h16.hl",
1274 "llvm.hexagon.A2.addh.h16.lh",
1275 "llvm.hexagon.A2.addh.h16.ll",
1276 "llvm.hexagon.A2.addh.h16.sat.hh",
1277 "llvm.hexagon.A2.addh.h16.sat.hl",
1278 "llvm.hexagon.A2.addh.h16.sat.lh",
1279 "llvm.hexagon.A2.addh.h16.sat.ll",
1323 "llvm.hexagon.A2.subh.h16.hh",
1324 "llvm.hexagon.A2.subh.h16.hl",
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td266 def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>;
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen706 hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.hh
707 hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.hl
708 hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.lh
709 hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.ll
710 hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.sat.hh
711 hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.sat.hl
712 hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.sat.lh
713 hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.sat.ll
757 hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.hh
758 hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.hl
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen706 hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.hh
707 hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.hl
708 hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.lh
709 hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.ll
710 hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.sat.hh
711 hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.sat.hl
712 hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.sat.lh
713 hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.sat.ll
757 hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.hh
758 hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.hl
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen706 hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.hh
707 hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.hl
708 hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.lh
709 hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.ll
710 hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.sat.hh
711 hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.sat.hl
712 hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.sat.lh
713 hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.sat.ll
757 hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.hh
758 hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.hl
[all …]
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen700 hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.hh
701 hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.hl
702 hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.lh
703 hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.ll
704 hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.sat.hh
705 hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.sat.hl
706 hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.sat.lh
707 hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.sat.ll
751 hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.hh
752 hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.hl
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen706 hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.hh
707 hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.hl
708 hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.lh
709 hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.ll
710 hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.sat.hh
711 hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.sat.hl
712 hexagon_A2_addh_h16_sat_lh, // llvm.hexagon.A2.addh.h16.sat.lh
713 hexagon_A2_addh_h16_sat_ll, // llvm.hexagon.A2.addh.h16.sat.ll
757 hexagon_A2_subh_h16_hh, // llvm.hexagon.A2.subh.h16.hh
758 hexagon_A2_subh_h16_hl, // llvm.hexagon.A2.subh.h16.hl
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td285 def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>;

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