| /external/mesa3d/src/gallium/drivers/nouveau/codegen/lib/ |
| D | gm107.asm | 23 imad u32 u32 hi $r2 $r2 $r3 $r2
25 imad u32 u32 hi $r2 $r2 $r3 $r2
28 imad u32 u32 hi $r2 $r2 $r3 $r2
31 imad u32 u32 hi $r2 $r2 $r3 $r2
33 imad u32 u32 hi $r2 $r2 $r3 $r2
39 imad u32 u32 $r1 $r1 $r0 $r3
72 imad u32 u32 hi $r2 $r2 $r3 $r2
75 imad u32 u32 hi $r2 $r2 $r3 $r2
77 imad u32 u32 hi $r2 $r2 $r3 $r2
80 imad u32 u32 hi $r2 $r2 $r3 $r2
[all …]
|
| /external/llvm/test/CodeGen/NVPTX/ |
| D | imad.ll | 3 ; CHECK: imad
4 define i32 @imad(i32 %a, i32 %b, i32 %c) {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/ |
| D | imad.ll | 3 ; CHECK: imad
4 define i32 @imad(i32 %a, i32 %b, i32 %c) {
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 623 def imad : SDNode<"NVPTXISD::IMAD", SDTIMAD>;
629 [(set Int16Regs:$dst, (imad Int16Regs:$a, Int16Regs:$b, Int16Regs:$c))]>;
634 [(set Int16Regs:$dst, (imad Int16Regs:$a, Int16Regs:$b, imm:$c))]>;
639 [(set Int16Regs:$dst, (imad Int16Regs:$a, imm:$b, Int16Regs:$c))]>;
644 [(set Int16Regs:$dst, (imad Int16Regs:$a, imm:$b, imm:$c))]>;
650 [(set Int32Regs:$dst, (imad Int32Regs:$a, Int32Regs:$b, Int32Regs:$c))]>;
655 [(set Int32Regs:$dst, (imad Int32Regs:$a, Int32Regs:$b, imm:$c))]>;
660 [(set Int32Regs:$dst, (imad Int32Regs:$a, imm:$b, Int32Regs:$c))]>;
665 [(set Int32Regs:$dst, (imad Int32Regs:$a, imm:$b, imm:$c))]>;
671 [(set Int64Regs:$dst, (imad Int64Regs:$a, Int64Regs:$b, Int64Regs:$c))]>;
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 726 def imad : SDNode<"NVPTXISD::IMAD", SDTIMAD>;
732 [(set Int16Regs:$dst, (imad Int16Regs:$a, Int16Regs:$b, Int16Regs:$c))]>;
737 [(set Int16Regs:$dst, (imad Int16Regs:$a, Int16Regs:$b, imm:$c))]>;
742 [(set Int16Regs:$dst, (imad Int16Regs:$a, imm:$b, Int16Regs:$c))]>;
747 [(set Int16Regs:$dst, (imad Int16Regs:$a, imm:$b, imm:$c))]>;
753 [(set Int32Regs:$dst, (imad Int32Regs:$a, Int32Regs:$b, Int32Regs:$c))]>;
758 [(set Int32Regs:$dst, (imad Int32Regs:$a, Int32Regs:$b, imm:$c))]>;
763 [(set Int32Regs:$dst, (imad Int32Regs:$a, imm:$b, Int32Regs:$c))]>;
768 [(set Int32Regs:$dst, (imad Int32Regs:$a, imm:$b, imm:$c))]>;
774 [(set Int64Regs:$dst, (imad Int64Regs:$a, Int64Regs:$b, Int64Regs:$c))]>;
[all …]
|
| /external/swiftshader/src/Shader/ |
| D | ShaderCore.hpp | 256 void imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2);
|
| D | VertexProgram.cpp | 223 case Shader::OPCODE_IMAD: imad(d, s0, s1, s2); break; in program()
|
| D | PixelProgram.cpp | 181 case Shader::OPCODE_IMAD: imad(d, s0, s1, s2); break; in applyShader()
|
| D | ShaderCore.cpp | 792 …void ShaderCore::imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &s… in imad() function in sw::ShaderCore
|
| /external/swiftshader/src/Pipeline/ |
| D | ShaderCore.hpp | 256 void imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2);
|
| D | VertexProgram.cpp | 216 case Shader::OPCODE_IMAD: imad(d, s0, s1, s2); break; in program()
|
| D | PixelProgram.cpp | 181 case Shader::OPCODE_IMAD: imad(d, s0, s1, s2); break; in applyShader()
|
| D | ShaderCore.cpp | 792 …void ShaderCore::imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &s… in imad() function in sw::ShaderCore
|