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Searched refs:imm12 (Results 1 – 25 of 28) sorted by relevance

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/external/vixl/test/aarch32/config/
Dcond-rd-rn-operand-imm12-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, #<imm12>
29 // MNEMONIC{<c>}.W <Rd>, SP, #<imm12>
33 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
34 // ADD{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
35 "Addw", // ADDW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
36 // ADDW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
37 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
38 // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
39 "Subw" // SUBW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
40 // SUBW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
[all …]
Dcond-rd-pc-operand-imm12-t32.json28 // MNEMONIC{<c>}.W <Rd>, PC, #<imm12>
32 "Add", // ADD{<c>}{<q>} <Rd>, PC, #<imm12> ; T3
33 "Addw", // ADDW{<c>}{<q>} <Rd>, PC, #<imm12> ; T3
34 "Sub" // SUB{<c>}{<q>} <Rd>, PC, #<imm12> ; T2
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td220 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
221 opcodestr, "$rs1, $rs2, $imm12"> {
228 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
229 opcodestr, "$rd, ${imm12}(${rs1})">;
237 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
238 opcodestr, "$rs2, ${imm12}(${rs1})">;
242 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
243 opcodestr, "$rd, $rs1, $imm12">;
258 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins uimm12:$imm12, GPR:$rs1),
259 opcodestr, "$rd, $imm12, $rs1">;
[all …]
DRISCVInstrFormats.td185 bits<12> imm12;
189 let Inst{31-20} = imm12;
233 bits<12> imm12;
237 let Inst{31-25} = imm12{11-5};
241 let Inst{11-7} = imm12{4-0};
248 bits<12> imm12;
252 let Inst{31} = imm12{11};
253 let Inst{30-25} = imm12{9-4};
257 let Inst{11-8} = imm12{3-0};
258 let Inst{7} = imm12{10};
DRISCVInstrInfoD.td71 (ins GPR:$rs1, simm12:$imm12),
72 "fld", "$rd, ${imm12}(${rs1})">;
79 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
80 "fsd", "$rs2, ${imm12}(${rs1})">;
DRISCVInstrInfoF.td92 (ins GPR:$rs1, simm12:$imm12),
93 "flw", "$rd, ${imm12}(${rs1})">;
100 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
101 "fsw", "$rs2, ${imm12}(${rs1})">;
/external/llvm/test/CodeGen/AArch64/
Darm64-addrmode.ll28 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
38 ; base + unsigned offset (> imm12 * size of type in bytes)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-addrmode.ll27 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
37 ; base + unsigned offset (> imm12 * size of type in bytes)
/external/v8/src/arm64/
Dassembler-arm64-inl.h1039 Instr Assembler::ImmLSUnsigned(int imm12) {
1040 DCHECK(is_uint12(imm12));
1041 return imm12 << ImmLSUnsigned_offset;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td609 // addrmode_imm12 := reg +/- imm12
677 // addrmode2 := reg +/- imm12
1416 let Inst{11-0} = addr{11-0}; // imm12
1446 let Inst{11-0} = addr{11-0}; // imm12
1477 let Inst{11-0} = addr{11-0}; // imm12
1506 let Inst{11-0} = addr{11-0}; // imm12
1688 let Inst{11-0} = addr{11-0}; // imm12
2174 let Inst{11-0} = addr{11-0}; // imm12
2232 // {11-0} imm12/Rm
2249 // {11-0} imm12/Rm
[all …]
DARMInstrFormats.td545 // {11-0} imm12/Rm
563 // {11-0} imm12/Rm
582 // {13} 1 == Rm, 0 == imm12
584 // {11-0} imm12/Rm
DREADME.txt510 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
DARMInstrThumb2.td115 // t2addrmode_imm12 := reg + imm12
126 // t2ldrlabel := imm12
873 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
952 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1477 let Inst{11-0} = addr{11-0}; // imm12
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td815 // addrmode_imm12 := reg +/- imm12
891 // addrmode2 := reg +/- imm12
1738 let Inst{11-0} = addr{11-0}; // imm12
1769 let Inst{11-0} = addr{11-0}; // imm12
1801 let Inst{11-0} = addr{11-0}; // imm12
1830 let Inst{11-0} = addr{11-0}; // imm12
2006 let Inst{11-0} = addr{11-0}; // imm12
2517 let Inst{11-0} = addr{11-0}; // imm12
2580 // {11-0} imm12/Rm
2598 // {11-0} imm12/Rm
[all …]
DARMInstrFormats.td674 // {11-0} imm12/Rm
692 // {11-0} imm12/Rm
711 // {13} 1 == Rm, 0 == imm12
713 // {11-0} imm12/Rm
DARMInstrThumb2.td151 // t2addrmode_imm12 := reg + imm12
162 // t2ldrlabel := imm12
973 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
1061 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1629 let Inst{11-0} = addr{11-0}; // imm12
1694 let Inst{11-0} = addr{11-0}; // imm12
DREADME.txt505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrInfo.td934 // addrmode_imm12 := reg +/- imm12
1842 let Inst{11-0} = addr{11-0}; // imm12
1873 let Inst{11-0} = addr{11-0}; // imm12
1905 let Inst{11-0} = addr{11-0}; // imm12
1934 let Inst{11-0} = addr{11-0}; // imm12
2113 let Inst{11-0} = addr{11-0}; // imm12
2627 let Inst{11-0} = addr{11-0}; // imm12
2690 // {11-0} imm12/Rm
2708 // {11-0} imm12/Rm
2800 // {11-0} imm12/Rm
[all …]
DARMInstrFormats.td694 // {11-0} imm12/Rm
712 // {11-0} imm12/Rm
731 // {13} 1 == Rm, 0 == imm12
733 // {11-0} imm12/Rm
DARMInstrThumb2.td154 // t2addrmode_imm12 := reg + imm12
165 // t2ldrlabel := imm12
979 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
1071 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1635 let Inst{11-0} = addr{11-0}; // imm12
1700 let Inst{11-0} = addr{11-0}; // imm12
DREADME.txt505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
/external/v8/src/arm/
Dassembler-arm.cc2164 void Assembler::ldr_pcrel(Register dst, int imm12, Condition cond) { in ldr_pcrel() argument
2166 if (imm12 < 0) { in ldr_pcrel()
2167 imm12 = -imm12; in ldr_pcrel()
2170 DCHECK(is_uint12(imm12)); in ldr_pcrel()
2171 emit(cond | B26 | am | L | pc.code() * B16 | dst.code() * B12 | imm12); in ldr_pcrel()
Dassembler-arm.h924 void ldr_pcrel(Register dst, int imm12, Condition cond = al);
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.h724 bool SetFlags, IValueT Rn, IValueT Rd, IValueT imm12,
/external/vixl/src/aarch64/
Dassembler-aarch64.h3725 static Instr ImmLSUnsigned(int64_t imm12) { in ImmLSUnsigned() argument
3726 VIXL_ASSERT(IsUint12(imm12)); in ImmLSUnsigned()
3727 return TruncateToUint12(imm12) << ImmLSUnsigned_offset; in ImmLSUnsigned()

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