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Searched refs:imm8 (Results 1 – 25 of 102) sorted by relevance

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/external/elfutils/libcpu/defs/
Di3868 %mask {imm8} 8
104 00001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m}
106 00001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m}
108 00001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m}
110 00001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m}
137 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg}
138 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg}
139 01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg}
140 00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg}
142 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg}
[all …]
/external/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-operand-immediate-t32.json30 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, #<imm8>
35 // ADD<c>{<q>} <Rdn>, #<imm8> ; T2
36 // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
38 // ADDS{<q>} <Rdn>, #<imm8> ; T2
39 // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
43 // SUB<c>{<q>} <Rdn>, #<imm8> ; T2
44 // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
46 // SUBS{<q>} <Rdn>, #<imm8> ; T2
47 // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
136 "Adds", // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
[all …]
Dcond-rdlow-operand-imm8-t32.json28 // MNEMONIC{<c>}.N <Rdn>, #<imm8>
32 "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
33 "Mov", // MOV<c>{<q>} <Rd>, #<imm8> ; T1
34 "Movs" // MOVS{<q>} <Rd>, #<imm8> ; T1
85 "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
86 "Mov" // MOV<c>{<q>} <Rd>, #<imm8> ; T1
Dcond-rd-pc-operand-imm8-t32.json28 // MNEMONIC{<c>}.W <Rd>, PC, #<imm8> ; wide encoding
32 "Add" // ADD{<c>}{<q>} <Rd>, PC, #<imm8> ; T1
Dcond-rd-sp-operand-imm8-t32.json28 // MNEMONIC{<c>}.N <rd>, SP #<imm8>
32 "Add" // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/
Dsimd16intrin.h52 #define _simd16_extract_ps(a, imm8) SIMD16::extract_ps<imm8>(a) argument
53 #define _simd16_extract_si(a, imm8) SIMD16::extract_si<imm8>(a) argument
54 #define _simd16_insert_ps(a, b, imm8) SIMD16::insert_ps<imm8>(a, b) argument
55 #define _simd16_insert_si(a, b, imm8) SIMD16::insert_si<imm8>(a, b) argument
150 #define _simd16_shuffle_epi32(a, b, imm8) SIMD16::shuffle_epi32<imm8>(a, b) argument
151 #define _simd16_shuffle_epi64(a, b, imm8) SIMD16::shuffle_epi64<imm8>(a, b) argument
Dsimdintrin.h162 #define _simd_shuffle_epi32(a, b, imm8) SIMD::shuffle_epi32<imm8>(a, b) argument
163 #define _simd_shuffle_epi64(a, b, imm8) SIMD::shuffle_epi64<imm8>(a, b) argument
/external/v8/src/x64/
Dassembler-x64.h793 void instruction##p(Register dst, Immediate imm8) { \
794 shift(dst, imm8, subcode, kPointerSize); \
797 void instruction##l(Register dst, Immediate imm8) { \
798 shift(dst, imm8, subcode, kInt32Size); \
801 void instruction##q(Register dst, Immediate imm8) { \
802 shift(dst, imm8, subcode, kInt64Size); \
805 void instruction##p(Operand dst, Immediate imm8) { \
806 shift(dst, imm8, subcode, kPointerSize); \
809 void instruction##l(Operand dst, Immediate imm8) { \
810 shift(dst, imm8, subcode, kInt32Size); \
[all …]
Dassembler-x64.cc1247 void Assembler::cmpb_al(Immediate imm8) { in cmpb_al() argument
1248 DCHECK(is_int8(imm8.value_) || is_uint8(imm8.value_)); in cmpb_al()
1251 emit(imm8.value_); in cmpb_al()
3087 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) { in extractps() argument
3089 DCHECK(is_uint8(imm8)); in extractps()
3097 emit(imm8); in extractps()
3100 void Assembler::pextrb(Register dst, XMMRegister src, int8_t imm8) { in pextrb() argument
3102 DCHECK(is_uint8(imm8)); in pextrb()
3110 emit(imm8); in pextrb()
3113 void Assembler::pextrb(Operand dst, XMMRegister src, int8_t imm8) { in pextrb() argument
[all …]
/external/v8/src/ia32/
Dassembler-ia32.cc872 void Assembler::cmpb(Operand op, Immediate imm8) { in cmpb() argument
873 DCHECK(imm8.is_int8() || imm8.is_uint8()); in cmpb()
881 emit_b(imm8); in cmpb()
1117 void Assembler::rcl(Register dst, uint8_t imm8) { in rcl() argument
1119 DCHECK(is_uint5(imm8)); // illegal shift count in rcl()
1120 if (imm8 == 1) { in rcl()
1126 EMIT(imm8); in rcl()
1131 void Assembler::rcr(Register dst, uint8_t imm8) { in rcr() argument
1133 DCHECK(is_uint5(imm8)); // illegal shift count in rcr()
1134 if (imm8 == 1) { in rcr()
[all …]
Dassembler-ia32.h585 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); } in mov_b() argument
670 void cmpb(Register reg, Immediate imm8) { cmpb(Operand(reg), imm8); } in cmpb() argument
671 void cmpb(Operand op, Immediate imm8);
732 void rcl(Register dst, uint8_t imm8);
733 void rcr(Register dst, uint8_t imm8);
735 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } in ror() argument
736 void ror(Operand dst, uint8_t imm8);
740 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); } in sar() argument
741 void sar(Operand dst, uint8_t imm8);
748 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); } in shl() argument
[all …]
Dmacro-assembler-ia32.h219 void ShlPair(Register high, Register low, uint8_t imm8);
221 void ShrPair(Register high, Register low, uint8_t imm8);
223 void SarPair(Register high, Register low, uint8_t imm8);
366 void Pblendw(XMMRegister dst, XMMRegister src, uint8_t imm8) { in Pblendw() argument
367 Pblendw(dst, Operand(src), imm8); in Pblendw()
369 void Pblendw(XMMRegister dst, Operand src, uint8_t imm8);
378 void Palignr(XMMRegister dst, XMMRegister src, uint8_t imm8) { in Palignr() argument
379 Palignr(dst, Operand(src), imm8); in Palignr()
381 void Palignr(XMMRegister dst, Operand src, uint8_t imm8);
383 void Pextrb(Register dst, XMMRegister src, int8_t imm8);
[all …]
Dmacro-assembler-ia32.cc1442 void TurboAssembler::Pblendw(XMMRegister dst, Operand src, uint8_t imm8) { in Pblendw() argument
1445 vpblendw(dst, dst, src, imm8); in Pblendw()
1450 pblendw(dst, src, imm8); in Pblendw()
1456 void TurboAssembler::Palignr(XMMRegister dst, Operand src, uint8_t imm8) { in Palignr() argument
1459 vpalignr(dst, dst, src, imm8); in Palignr()
1464 palignr(dst, src, imm8); in Palignr()
1470 void TurboAssembler::Pextrb(Register dst, XMMRegister src, int8_t imm8) { in Pextrb() argument
1473 vpextrb(dst, src, imm8); in Pextrb()
1478 pextrb(dst, src, imm8); in Pextrb()
1484 void TurboAssembler::Pextrw(Register dst, XMMRegister src, int8_t imm8) { in Pextrw() argument
[all …]
Ddisasm-ia32.cc627 int imm8 = -1; in D1D3C1Instruction() local
657 imm8 = 1; in D1D3C1Instruction()
659 imm8 = *(data + 1); in D1D3C1Instruction()
664 if (imm8 >= 0) { in D1D3C1Instruction()
665 AppendToBuffer(",%d", imm8); in D1D3C1Instruction()
1746 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
1750 static_cast<int>(imm8)); in InstructionDecode()
1773 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
1776 NameOfCPURegister(regop), static_cast<int>(imm8)); in InstructionDecode()
1992 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
[all …]
/external/epid-sdk/ext/ipp/sources/include/
Dia_32e.inc575 sha1rnds4 MACRO op1:req, op2:req, imm8:req
576 %ECHO @CatStr(<sha1rnds4 >, < op1,>, < op2,>, < imm8 >)
2331 mni_instruction macro dst:req, src:req, nis:req, opc:req, imm8
2368 IFNB <imm8>
2372 db imm8
2384 IFNB <imm8>
2388 db imm8
2405 IFNB <imm8>
2406 db imm8
2417 IFNB <imm8>
[all …]
Dia_emm.inc147 sha1rnds4 MACRO op1:req, op2:req, imm8:req
148 %ECHO @CatStr(<sha1rnds4 >, < op1,>, < op2,>, < imm8 >)
1680 palignr macro dst:req, src:req, imm8:req
1682 db imm8
1711 nis_snia = 3Ah ; new instruction set 'a' (with imm8)
1833 ; 66 0F 3A 0D blendpd xmm1, xmm2/m128, imm8
1834 blendpd macro dst:req, src:req, imm8:req
1836 db imm8
1840 ; 66 0F 3A 0C blendps xmm1, xmm2/m128, imm8
1841 blendps macro dst:req, src:req, imm8:req
[all …]
/external/vixl/src/aarch32/
Dinstructions-aarch32.cc629 uint32_t imm8 = imm >> (24 - shift); in ImmediateT32() local
631 if ((imm8 <= 0xff) && ((imm8 & 0x80) != 0) && (overflow == 0)) { in ImmediateT32()
632 SetEncodingValue(((shift + 8) << 7) | (imm8 & 0x7F)); in ImmediateT32()
686 uint32_t imm8 = (imm << rot) | (imm >> (32 - rot)); in ImmediateA32() local
687 if (imm8 <= 0xff) { in ImmediateA32()
688 SetEncodingValue((rot << 7) | imm8); in ImmediateA32()
/external/vixl/src/aarch64/
Dinstructions-aarch64.cc165 Float16 Instruction::Imm8ToFloat16(uint32_t imm8) { in Imm8ToFloat16() argument
169 uint32_t bits = imm8; in Imm8ToFloat16()
178 float Instruction::Imm8ToFP32(uint32_t imm8) { in Imm8ToFP32() argument
182 uint32_t bits = imm8; in Imm8ToFP32()
198 double Instruction::Imm8ToFP64(uint32_t imm8) { in Imm8ToFP64() argument
203 uint32_t bits = imm8; in Imm8ToFP64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb.td169 // t_addrmode_pc := <label> => pc + imm8 * 4
259 // t_addrmode_sp := sp + imm8 * 4
383 // ADD <Rd>, sp, #<imm8>
919 bits<8> imm8;
921 let Inst{7-0} = imm8;
945 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
946 "add", "\t$Rdn, $imm8",
947 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
979 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
982 imm8_255:$imm8))]>,
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td160 // t_addrmode_pc := <label> => pc + imm8 * 4
250 // t_addrmode_sp := sp + imm8 * 4
366 // ADD <Rd>, sp, #<imm8>
902 bits<8> imm8;
904 let Inst{7-0} = imm8;
927 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
928 "add", "\t$Rdn, $imm8",
929 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
1006 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
1007 "cmp", "\t$Rn, $imm8",
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb.td204 // t_addrmode_sp := sp + imm8 * 4
218 // t_addrmode_pc := <label> => pc + imm8 * 4
312 // ADD <Rd>, sp, #<imm8>
851 bits<8> imm8;
853 let Inst{7-0} = imm8;
875 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
876 "add", "\t$Rdn, $imm8",
877 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
951 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
952 "cmp", "\t$Rn, $imm8",
[all …]
/external/v8/src/arm64/
Dinstructions-arm64.h181 static float Imm8ToFP32(uint32_t imm8) { in Imm8ToFP32() argument
185 uint32_t bits = imm8; in Imm8ToFP32()
194 static double Imm8ToFP64(uint32_t imm8) { in Imm8ToFP64() argument
199 uint32_t bits = imm8; in Imm8ToFP64()
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td115 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
123 bits<8> imm8;
128 let Inst{7-0} = imm8;
315 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
323 bits<8> imm8;
329 let Inst{7-0} = imm8;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td115 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
123 bits<8> imm8;
128 let Inst{7-0} = imm8;
315 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
323 bits<8> imm8;
329 let Inst{7-0} = imm8;
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td18 def imm8 : RTLNode;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;

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