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Searched refs:instr1 (Results 1 – 23 of 23) sorted by relevance

/external/tensorflow/tensorflow/compiler/xla/service/
Dmulti_output_fusion.cc113 HloInstruction* MultiOutputFusion::Fuse(HloInstruction* instr1, in Fuse() argument
115 HloInstruction* remaining = instr1; in Fuse()
150 void MultiOutputFusion::Update(HloInstruction* instr1, HloInstruction* instr2) { in Update() argument
151 HloInstruction* fusion = instr1; in Update()
153 if (is_fused(instr1)) { in Update()
155 fused = instr1; in Update()
216 bool MultiOutputFusion::LegalToFuse(HloInstruction* instr1, in LegalToFuse() argument
218 if (instr1 == instr2) { in LegalToFuse()
221 if (instr1->opcode() != HloOpcode::kFusion) { in LegalToFuse()
227 if (instr1->user_count() == 0 || instr2->user_count() == 0) { in LegalToFuse()
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Dmulti_output_fusion.h65 virtual bool ShapesCompatibleForFusion(HloInstruction* instr1,
73 virtual int64 GetProfit(HloInstruction* instr1, HloInstruction* instr2) = 0;
79 virtual bool LegalToFuse(HloInstruction* instr1, HloInstruction* instr2);
83 virtual HloInstruction* Fuse(HloInstruction* instr1, HloInstruction* instr2);
96 HloInstruction* instr1, HloInstruction* instr2,
116 void Update(HloInstruction* instr1, HloInstruction* instr2);
141 HloInstruction* instr1; member
144 ToBeFused(HloInstruction* instr1, HloInstruction* instr2, int64 score) in ToBeFused()
145 : instr1(instr1), instr2(instr2), score(score) {} in ToBeFused()
162 bool is_connected(HloInstruction* instr1, HloInstruction* instr2) { in is_connected() argument
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Dhlo_verifier.cc1082 Status CheckSameChannel(const HloInstruction* instr1, in CheckSameChannel() argument
1084 if (instr1->channel_id() != instr2->channel_id()) { in CheckSameChannel()
1088 instr1->ToString(), instr1->channel_id(), instr2->ToString(), in CheckSameChannel()
1097 Status CheckSameIsHostTransfer(const HloInstruction* instr1, in CheckSameIsHostTransfer() argument
1100 DynCast<const HloSendRecvInstruction>(instr1); in CheckSameIsHostTransfer()
1110 instr1->ToString(), instr2->ToString()); in CheckSameIsHostTransfer()
Dhlo_instruction_test.cc1696 auto instr1 = HloInstruction::CreateCustomCall(ShapeUtil::MakeShape(F32, {}), in TEST_F() local
1699 auto instr2 = instr1->Clone(); in TEST_F()
1700 EXPECT_TRUE(instr1->Identical(*instr2)); in TEST_F()
1703 instr1->set_window(w); in TEST_F()
1704 EXPECT_FALSE(instr1->Identical(*instr2)); in TEST_F()
1708 auto instr1 = HloInstruction::CreateCustomCall(ShapeUtil::MakeShape(F32, {}), in TEST_F() local
1711 auto instr2 = instr1->Clone(); in TEST_F()
1712 EXPECT_TRUE(instr1->Identical(*instr2)); in TEST_F()
1716 instr1->set_convolution_dimension_numbers(dnums); in TEST_F()
1717 EXPECT_FALSE(instr1->Identical(*instr2)); in TEST_F()
/external/compiler-rt/test/profile/
Dinstrprof-shared.test5 2. libt-no-instr1.so is not instrumented
18 RUN: %clang -o %t.d/libt-no-instr1.so -fPIC -shared %S/Inputs/instrprof-shared-lib.c
23 RUN: %clang_profgen -o %t-instr-no-instr1 -L%t.d -rpath %t.d -lt-no-instr1 %S/Inputs/instrprof-sha…
25 RUN: %clang -o %t-no-instr1-instr -L%t.d -rpath %t.d -lt-instr %S/Inputs/instrprof-shared-main.c
26 RUN: %clang -o %t-no-instr1-no-instr1 -L%t.d -rpath %t.d -lt-no-instr1 %S/Inputs/instrprof-shared-…
27 RUN: %clang -o %t-no-instr1-no-instr2 -L%t.d -rpath %t.d -lt-no-instr2 %S/Inputs/instrprof-shared-…
30 RUN: %clang -o %t-no-instr2-no-instr1 -L%t.d -rpath %t.d -lt-no-instr1 %t.d/instrprof-shared-main-…
34 RUN: env LLVM_PROFILE_FILE=%t-instr-no-instr1.profraw %run %t-instr-no-instr1
36 RUN: env LLVM_PROFILE_FILE=%t-no-instr1-instr.profraw %run %t-no-instr1-instr
38 RUN: env LLVM_PROFILE_FILE=%t-no-instr1-no-instr1.profraw %run %t-no-instr1-no-instr1
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/external/tensorflow/tensorflow/compiler/xla/service/gpu/
Dmulti_output_fusion.cc42 bool GpuMultiOutputFusion::ShapesCompatibleForFusion(HloInstruction* instr1, in ShapesCompatibleForFusion() argument
44 return ShapesCompatibleForMultiOutputFusion(*instr1, *instr2); in ShapesCompatibleForFusion()
59 int64 GpuMultiOutputFusion::GetProfit(HloInstruction* instr1, in GetProfit() argument
62 for (auto instr : instr1->operands()) { in GetProfit()
75 VLOG(2) << "Fusing instr1=" << instr1->name() << " instr2=" << instr2->name() in GetProfit()
80 bool GpuMultiOutputFusion::LegalToFuse(HloInstruction* instr1, in LegalToFuse() argument
82 if (!MultiOutputFusion::LegalToFuse(instr1, instr2)) { in LegalToFuse()
92 CHECK(instr1->opcode() == HloOpcode::kFusion); in LegalToFuse()
94 instr1->fusion_kind() != instr2->fusion_kind()) || in LegalToFuse()
96 instr1->fusion_kind() == HloInstruction::FusionKind::kLoop)) { in LegalToFuse()
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Dmulti_output_fusion.h33 bool ShapesCompatibleForFusion(HloInstruction* instr1,
44 int64 GetProfit(HloInstruction* instr1, HloInstruction* instr2) override;
47 bool LegalToFuse(HloInstruction* instr1, HloInstruction* instr2) override;
Dgpu_fusible.cc89 bool ShapesCompatibleForMultiOutputFusion(const HloInstruction& instr1, in ShapesCompatibleForMultiOutputFusion() argument
127 auto* instr_1 = get_real_hero(&instr1); in ShapesCompatibleForMultiOutputFusion()
Dgpu_fusible.h69 bool ShapesCompatibleForMultiOutputFusion(const HloInstruction& instr1,
/external/v8/src/ppc/
Dassembler-ppc-inl.h279 Instr instr1 = instr_at(pc); in target_address_at() local
282 if (IsLis(instr1) && IsOri(instr2)) { in target_address_at()
287 uint64_t hi = (static_cast<uint32_t>((instr1 & kImm16Mask) << 16) | in target_address_at()
294 return static_cast<Address>(((instr1 & kImm16Mask) << 16) | in target_address_at()
397 Instr instr1 = instr_at(pc); in PatchConstantPoolAccessInstruction() local
399 instr1 &= ~kImm16Mask; in PatchConstantPoolAccessInstruction()
400 instr1 |= (hi_word & kImm16Mask); in PatchConstantPoolAccessInstruction()
403 instr_at_put(pc, instr1); in PatchConstantPoolAccessInstruction()
462 Instr instr1 = instr_at(pc); in set_target_address_at() local
465 if (IsLis(instr1) && IsOri(instr2)) { in set_target_address_at()
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Dassembler-ppc.cc338 bool Assembler::Is64BitLoadIntoR12(Instr instr1, Instr instr2, Instr instr3, in Is64BitLoadIntoR12() argument
346 return (((instr1 >> 16) == 0x3D80) && ((instr2 >> 16) == 0x618C) && in Is64BitLoadIntoR12()
352 bool Assembler::Is32BitLoadIntoR12(Instr instr1, Instr instr2) { in Is32BitLoadIntoR12() argument
356 return (((instr1 >> 16) == 0x3D80) && ((instr2 >> 16) == 0x618C)); in Is32BitLoadIntoR12()
Dassembler-ppc.h1381 static bool Is64BitLoadIntoR12(Instr instr1, Instr instr2, Instr instr3,
1384 static bool Is32BitLoadIntoR12(Instr instr1, Instr instr2);
/external/v8/src/mips/
Dassembler-mips-inl.h144 Instr instr1 = Assembler::instr_at(pc + 0 * kInstrSize); in set_target_internal_reference_encoded_at() local
146 DCHECK(Assembler::IsLui(instr1)); in set_target_internal_reference_encoded_at()
148 instr1 &= ~kImm16Mask; in set_target_internal_reference_encoded_at()
157 Assembler::instr_at_put(pc + 0 * kInstrSize, instr1 | lui_offset_u); in set_target_internal_reference_encoded_at()
162 instr1 | ((imm >> kLuiShift) & kImm16Mask)); in set_target_internal_reference_encoded_at()
225 Instr instr1 = Assembler::instr_at(pc_ + 0 * kInstrSize); in target_internal_reference() local
227 DCHECK(Assembler::IsLui(instr1)); in target_internal_reference()
231 Assembler::CreateTargetAddress(instr1, instr2)); in target_internal_reference()
233 int32_t imm = (instr1 & static_cast<int32_t>(kImm16Mask)) << kLuiShift; in target_internal_reference()
Dassembler-mips.cc891 Instr instr1 = instr_at(pos + 0 * kInstrSize); in target_at() local
896 imm = CreateTargetAddress(instr1, instr2); in target_at()
898 imm = (instr1 & static_cast<int32_t>(kImm16Mask)) << kLuiShift; in target_at()
1019 Instr instr1 = instr_at(pos + 0 * kInstrSize); in target_at_put() local
1024 DCHECK(IsLui(instr1) && (IsJicOrJialc(instr2) || IsOri(instr2))); in target_at_put()
1025 instr1 &= ~kImm16Mask; in target_at_put()
1031 instr_at_put(pos + 0 * kInstrSize, instr1 | lui_offset_u); in target_at_put()
1035 instr1 | ((imm & kHiMask) >> kLuiShift)); in target_at_put()
3754 Instr instr1 = instr_at(pc + 0 * kInstrSize); in MSA_BIT_LIST() local
3759 imm = CreateTargetAddress(instr1, instr2); in MSA_BIT_LIST()
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/external/mesa3d/src/compiler/nir/
Dnir_instr_set.c254 nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2) in nir_instrs_equal() argument
256 if (instr1->type != instr2->type) in nir_instrs_equal()
259 switch (instr1->type) { in nir_instrs_equal()
261 nir_alu_instr *alu1 = nir_instr_as_alu(instr1); in nir_instrs_equal()
293 nir_tex_instr *tex1 = nir_instr_as_tex(instr1); in nir_instrs_equal()
327 nir_load_const_instr *load1 = nir_instr_as_load_const(instr1); in nir_instrs_equal()
340 nir_phi_instr *phi1 = nir_instr_as_phi(instr1); in nir_instrs_equal()
360 nir_intrinsic_instr *intrinsic1 = nir_instr_as_intrinsic(instr1); in nir_instrs_equal()
/external/tensorflow/tensorflow/compiler/tf2xla/
Dxla_compiler_test.cc707 auto instr1 = c1.instructions(j); in TEST_F() local
709 instr1.clear_name(); in TEST_F()
710 instr1.clear_id(); in TEST_F()
711 instr1.clear_operand_ids(); in TEST_F()
719 LOG(INFO) << "instr1 = " << instr1.DebugString(); in TEST_F()
721 instr1.AppendPartialToString(&str1); in TEST_F()
/external/v8/src/s390/
Dassembler-s390.cc398 bool Assembler::Is64BitLoadIntoIP(SixByteInstr instr1, SixByteInstr instr2) { in Is64BitLoadIntoIP() argument
400 return (((instr1 >> 32) == 0xC0C8) && ((instr2 >> 32) == 0xC0C9)); in Is64BitLoadIntoIP()
Dassembler-s390.h1535 static bool Is64BitLoadIntoIP(SixByteInstr instr1, SixByteInstr instr2);
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DMergeFunctions.rst415 instr0 i32 %pf0 instr1 i32 %pf1 instr2 i32 123
421 instr0 i32 %pg0 instr1 i32 %pg0 instr2 i32 123
430 Instruction with opcode "*instr1*" from *f* is *greater* than instruction with
431 opcode "*instr1*" from *g*; here we have equal types and opcodes, but "*pf1* is
/external/llvm/docs/
DMergeFunctions.rst415 instr0 i32 %pf0 instr1 i32 %pf1 instr2 i32 123
421 instr0 i32 %pg0 instr1 i32 %pg0 instr2 i32 123
430 Instruction with opcode "*instr1*" from *f* is *greater* than instruction with
431 opcode "*instr1*" from *g*; here we have equal types and opcodes, but "*pf1* is
/external/v8/src/mips64/
Dassembler-mips64.cc4314 Instr instr1 = instr_at(pc + 1 * kInstrSize); in target_address_at() local
4319 if ((GetOpcodeField(instr0) == LUI) && (GetOpcodeField(instr1) == ORI) && in target_address_at()
4324 ((uint64_t)(GetImmediate16(instr1)) << 16) | in target_address_at()
4364 Instr instr1 = instr_at(pc + kInstrSize); in set_target_value_at() local
4365 uint32_t rt_code = GetRt(instr1); in set_target_value_at()
4372 DCHECK((GetOpcodeField(instr0) == LUI && GetOpcodeField(instr1) == ORI && in set_target_value_at()
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc419 #define ASSEMBLE_ATOMIC64_ARITH_BINOP(instr1, instr2) \ argument
426 __ instr1(i.TempRegister(1), i.OutputRegister(0), i.InputRegister(0), \
2790 #define ATOMIC_ARITH_BINOP_CASE(op, instr1, instr2) \ in AssembleArchInstruction() argument
2792 ASSEMBLE_ATOMIC64_ARITH_BINOP(instr1, instr2); \ in AssembleArchInstruction()
/external/v8/src/compiler/ia32/
Dcode-generator-ia32.cc430 #define ASSEMBLE_I64ATOMIC_BINOP(instr1, instr2) \ argument
438 __ instr1(i.InputRegister(0), i.OutputRegister(0)); \
3807 #define ATOMIC_BINOP_CASE(op, instr1, instr2) \ in AssembleArchInstruction() argument
3809 ASSEMBLE_I64ATOMIC_BINOP(instr1, instr2) \ in AssembleArchInstruction()