Searched refs:is16BitMode (Results 1 – 8 of 8) sorted by relevance
142 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) { in getRelaxedOpcodeBranch() argument148 return (is16BitMode) ? X86::JAE_2 : X86::JAE_4; in getRelaxedOpcodeBranch()150 return (is16BitMode) ? X86::JA_2 : X86::JA_4; in getRelaxedOpcodeBranch()152 return (is16BitMode) ? X86::JBE_2 : X86::JBE_4; in getRelaxedOpcodeBranch()154 return (is16BitMode) ? X86::JB_2 : X86::JB_4; in getRelaxedOpcodeBranch()156 return (is16BitMode) ? X86::JE_2 : X86::JE_4; in getRelaxedOpcodeBranch()158 return (is16BitMode) ? X86::JGE_2 : X86::JGE_4; in getRelaxedOpcodeBranch()160 return (is16BitMode) ? X86::JG_2 : X86::JG_4; in getRelaxedOpcodeBranch()162 return (is16BitMode) ? X86::JLE_2 : X86::JLE_4; in getRelaxedOpcodeBranch()164 return (is16BitMode) ? X86::JL_2 : X86::JL_4; in getRelaxedOpcodeBranch()[all …]
52 bool is16BitMode(const MCSubtargetInfo &STI) const { in is16BitMode() function in __anonc84e4ccd0111::X86MCCodeEmitter64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()1064 if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32 in emitOpcodePrefix()1164 if ((is16BitMode(STI) && AdSize == X86II::AdSize32) || in encodeInstruction()1177 assert(is16BitMode(STI)); in encodeInstruction()
135 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) { in getRelaxedOpcodeBranch() argument141 return (is16BitMode) ? X86::JAE_2 : X86::JAE_4; in getRelaxedOpcodeBranch()143 return (is16BitMode) ? X86::JA_2 : X86::JA_4; in getRelaxedOpcodeBranch()145 return (is16BitMode) ? X86::JBE_2 : X86::JBE_4; in getRelaxedOpcodeBranch()147 return (is16BitMode) ? X86::JB_2 : X86::JB_4; in getRelaxedOpcodeBranch()149 return (is16BitMode) ? X86::JE_2 : X86::JE_4; in getRelaxedOpcodeBranch()151 return (is16BitMode) ? X86::JGE_2 : X86::JGE_4; in getRelaxedOpcodeBranch()153 return (is16BitMode) ? X86::JG_2 : X86::JG_4; in getRelaxedOpcodeBranch()155 return (is16BitMode) ? X86::JLE_2 : X86::JLE_4; in getRelaxedOpcodeBranch()157 return (is16BitMode) ? X86::JL_2 : X86::JL_4; in getRelaxedOpcodeBranch()[all …]
60 bool is16BitMode(const MCSubtargetInfo &STI) const { in is16BitMode() function in __anonce9fbb050111::X86MCCodeEmitter72 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()1136 if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32 in emitOpcodePrefix()1243 if ((is16BitMode(STI) && AdSize == X86II::AdSize32) || in encodeInstruction()1256 assert(is16BitMode(STI)); in encodeInstruction()
905 bool is16BitMode() const { in is16BitMode() function in __anonfb2428c60111::X86AsmParser921 if (is16BitMode()) return 16; in getPointerWidth()2488 if (PatchedName == "data16" && is16BitMode()) { in ParseInstruction()2572 if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) { in ParseInstruction()2573 Name = is16BitMode() ? "movw" : "movl"; in ParseInstruction()2578 getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32); in ParseInstruction()3153 : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " "; in MatchAndEmitIntelInstruction()3351 if (!is16BitMode()) { in ParseDirectiveCode()3359 if (!is16BitMode()) { in ParseDirectiveCode()
274 bool is16BitMode() const { in is16BitMode() function in __anon253bcfad0111::X86AddressSanitizer279 if (is16BitMode()) return 16; in getPointerWidth()
261 bool is16BitMode() const { in is16BitMode() function in llvm::__anon44d5f3750111::X86AddressSanitizer266 if (is16BitMode()) return 16; in getPointerWidth()
768 bool is16BitMode() const { in is16BitMode() function in __anon720aab8e0111::X86AsmParser784 if (is16BitMode()) return 16; in getPointerWidth()3006 if (!is16BitMode()) { in ParseDirectiveCode()