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Searched refs:isLd (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp837 bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD; in MergeBaseUpdateLoadStore() local
840 if (isLd && MI->getOperand(0).getReg() == Base) in MergeBaseUpdateLoadStore()
904 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
906 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
908 } else if (isLd) { in MergeBaseUpdateLoadStore()
1083 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp() local
1084 bool EvenDeadKill = isLd ? in FixInvalidRegPairOp()
1087 bool OddDeadKill = isLd ? in FixInvalidRegPairOp()
1103 unsigned NewOpc = (isLd) in FixInvalidRegPairOp()
1106 if (isLd) { in FixInvalidRegPairOp()
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DARMInstrFormats.td512 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
522 let Inst{20} = isLd;
525 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
535 let Inst{20} = isLd; // L bit
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1379 bool isLd = isLoadSingle(Opcode); in MergeBaseUpdateLoadStore() local
1388 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
1390 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1392 } else if (isLd) { in MergeBaseUpdateLoadStore()
1598 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp() local
1599 bool EvenDeadKill = isLd ? in FixInvalidRegPairOp()
1602 bool OddDeadKill = isLd ? in FixInvalidRegPairOp()
1616 unsigned NewOpc = (isLd) in FixInvalidRegPairOp()
1619 if (isLd) { in FixInvalidRegPairOp()
1623 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
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DARMInstrFormats.td641 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
651 let Inst{20} = isLd;
654 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
664 let Inst{20} = isLd; // L bit
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1413 bool isLd = isLoadSingle(Opcode); in MergeBaseUpdateLoadStore() local
1422 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
1424 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1426 } else if (isLd) { in MergeBaseUpdateLoadStore()
1640 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp() local
1641 bool EvenDeadKill = isLd ? in FixInvalidRegPairOp()
1644 bool OddDeadKill = isLd ? in FixInvalidRegPairOp()
1658 unsigned NewOpc = (isLd) in FixInvalidRegPairOp()
1661 if (isLd) { in FixInvalidRegPairOp()
1665 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
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DARMInstrFormats.td661 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
671 let Inst{20} = isLd;
674 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
684 let Inst{20} = isLd; // L bit