| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSubtarget.h | 236 bool isMClass() const { return IsMClass; } in isMClass() function
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| D | ARMInstrInfo.td | 208 def IsMClass : Predicate<"Subtarget->isMClass()">,
210 def IsARClass : Predicate<"!Subtarget->isMClass()">,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.h | 552 bool isMClass() const { return ARMProcClass == MClass; } in isMClass() function
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| D | ARMBaseRegisterInfo.cpp | 75 if (STI.isMClass()) { in getCalleeSavedRegs()
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| D | ARMAsmPrinter.cpp | 596 if (Subtarget->isMClass() && Subtarget->hasDSP()) in getArchForCPU()
669 } else if (STI.isMClass()) { in emitAttributes()
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| D | ARMBaseInstrInfo.cpp | 682 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
690 if (Subtarget.isMClass()) in copyFromCPSR()
703 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
708 if (Subtarget.isMClass()) in copyToCPSR()
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| D | ARMISelLowering.cpp | 854 if (!Subtarget->isThumb() || !Subtarget->isMClass()) in ARMTargetLowering()
1283 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4); in shouldAlignPointerArgs()
1811 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass()); in LowerCall()
2372 !Subtarget->isMClass()) { in LowerReturn()
3016 if (Subtarget->isMClass()) { in LowerATOMIC_FENCE()
12348 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; in makeDMB()
12404 return (Size == 64) && !Subtarget->isMClass(); in shouldExpandAtomicStoreInIR()
12417 return ((Size == 64) && !Subtarget->isMClass()) ? AtomicExpansionKind::LLOnly in shouldExpandAtomicLoadInIR()
12426 return (Size <= (Subtarget->isMClass() ? 32U : 64U)) in shouldExpandAtomicRMWInIR()
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| D | ARMISelDAGToDAG.cpp | 4033 if (Subtarget->isMClass()) { in tryReadRegister()
4150 if (Subtarget->isMClass()) { in tryWriteRegister()
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| D | ARMInstrInfo.td | 285 def IsMClass : Predicate<"Subtarget->isMClass()">,
287 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.h | 698 bool isMClass() const { return ARMProcClass == MClass; } in isMClass() function
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| D | ARMBaseRegisterInfo.cpp | 80 if (STI.isMClass()) { in getCalleeSavedRegs()
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| D | ARMTargetTransformInfo.cpp | 571 if (!ST->isMClass()) in getUnrollingPreferences()
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| D | ARMBaseInstrInfo.cpp | 770 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
778 if (Subtarget.isMClass()) in copyFromCPSR()
790 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
795 if (Subtarget.isMClass()) in copyToCPSR()
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| D | ARMISelLowering.cpp | 975 if (!Subtarget->isThumb() || !Subtarget->isMClass()) in ARMTargetLowering()
1426 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4); in shouldAlignPointerArgs()
2005 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass()); in LowerCall()
2597 !Subtarget->isMClass()) { in LowerReturn()
3449 if (Subtarget->isMClass()) { in LowerATOMIC_FENCE()
14331 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; in makeDMB()
14387 return (Size == 64) && !Subtarget->isMClass(); in shouldExpandAtomicStoreInIR()
14400 return ((Size == 64) && !Subtarget->isMClass()) ? AtomicExpansionKind::LLOnly in shouldExpandAtomicLoadInIR()
14410 return (Size <= (Subtarget->isMClass() ? 32U : 64U) && hasAtomicRMW) in shouldExpandAtomicRMWInIR()
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| D | ARMISelDAGToDAG.cpp | 3993 if (Subtarget->isMClass()) { in tryReadRegister()
4104 if (Subtarget->isMClass()) { in tryWriteRegister()
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| D | ARMInstrInfo.td | 327 def IsMClass : Predicate<"Subtarget->isMClass()">,
329 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 513 bool isMClass() const { in isMClass() function in __anon7876b5fa0111::ARMAsmParser
4365 if (isMClass()) { in parseMSRMaskOperand()
6146 } else if (Mnemonic == "cps" && isMClass()) { in ParseInstruction()
6710 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
10451 if (isMClass() && (MissingFeatures & Feature_HasNEON)) in FilterNearMisses()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 124 bool isMClass() const { in isMClass() function in __anon92cf716e0111::ARMAsmParser
2338 if (isMClass()) { in parseMSRMaskOperand()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 309 bool isMClass() const { in isMClass() function in __anonef5d38c20111::ARMAsmParser
4051 if (isMClass()) { in parseMSRMaskOperand()
5924 } else if (Mnemonic == "cps" && isMClass()) { in ParseInstruction()
6458 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenDAGISel.inc | 27688 /* 60633*/ OPC_CheckPatternPredicate, 55, // (!Subtarget->isMClass()) && (Subtarget->isThumb2(…
39349 case 55: return (!Subtarget->isMClass()) && (Subtarget->isThumb2());
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| D | ARMGenGlobalISel.inc | 185 if (!Subtarget->isMClass())
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