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Searched refs:isSubClassOf (Results 1 – 25 of 73) sorted by relevance

123

/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DPredicateExpander.cpp37 assert(Reg->isSubClassOf("Register") && "Expected a register Record!"); in expandCheckRegOperand()
186 if (Rec->isSubClassOf("MCTrue")) { in expandPredicate()
192 if (Rec->isSubClassOf("MCFalse")) { in expandPredicate()
198 if (Rec->isSubClassOf("CheckNot")) { in expandPredicate()
205 if (Rec->isSubClassOf("CheckIsRegOperand")) in expandPredicate()
208 if (Rec->isSubClassOf("CheckIsImmOperand")) in expandPredicate()
211 if (Rec->isSubClassOf("CheckRegOperand")) in expandPredicate()
215 if (Rec->isSubClassOf("CheckInvalidRegOperand")) in expandPredicate()
218 if (Rec->isSubClassOf("CheckImmOperand")) in expandPredicate()
222 if (Rec->isSubClassOf("CheckImmOperand_s")) in expandPredicate()
[all …]
DCallingConvEmitter.cpp85 if (Action->isSubClassOf("CCPredicateAction")) { in EmitAction()
88 if (Action->isSubClassOf("CCIfType")) { in EmitAction()
96 } else if (Action->isSubClassOf("CCIf")) { in EmitAction()
107 if (Action->isSubClassOf("CCDelegateTo")) { in EmitAction()
112 } else if (Action->isSubClassOf("CCAssignToReg")) { in EmitAction()
133 } else if (Action->isSubClassOf("CCAssignToRegWithShadow")) { in EmitAction()
174 } else if (Action->isSubClassOf("CCAssignToStack")) { in EmitAction()
198 } else if (Action->isSubClassOf("CCAssignToStackWithShadow")) { in EmitAction()
221 } else if (Action->isSubClassOf("CCPromoteToType")) { in EmitAction()
235 } else if (Action->isSubClassOf("CCPromoteToUpperBitsInType")) { in EmitAction()
[all …]
DDAGISelMatcherGen.cpp235 if (LeafRec->isSubClassOf("ValueType")) { in EmitLeafMatchCode()
244 LeafRec->isSubClassOf("RegisterClass") || in EmitLeafMatchCode()
245 LeafRec->isSubClassOf("RegisterOperand") || in EmitLeafMatchCode()
246 LeafRec->isSubClassOf("PointerLikeRegClass") || in EmitLeafMatchCode()
247 LeafRec->isSubClassOf("SubRegIndex") || in EmitLeafMatchCode()
254 if (LeafRec->isSubClassOf("Register")) { in EmitLeafMatchCode()
261 if (LeafRec->isSubClassOf("CondCode")) in EmitLeafMatchCode()
264 if (LeafRec->isSubClassOf("ComplexPattern")) { in EmitLeafMatchCode()
290 if (N->getOperator()->isSubClassOf("ComplexPattern")) { in EmitOperatorMatchCode()
622 if (Def->isSubClassOf("Register")) { in EmitResultLeafAsOperand()
[all …]
DCodeGenInstruction.cpp76 if (Rec->isSubClassOf("RegisterOperand")) { in CGIOperandList()
81 } else if (Rec->isSubClassOf("Operand")) { in CGIOperandList()
100 if (Rec->isSubClassOf("PredicateOp")) in CGIOperandList()
102 else if (Rec->isSubClassOf("OptionalDefOperand")) in CGIOperandList()
107 } else if (Rec->isSubClassOf("RegisterClass")) { in CGIOperandList()
109 } else if (!Rec->isSubClassOf("PointerLikeRegClass") && in CGIOperandList()
110 !Rec->isSubClassOf("unknown_class")) in CGIOperandList()
384 assert(FirstImplicitDef->isSubClassOf("Register")); in HasOneImplicitDefWithKnownVT()
444 return Constraint->getDef()->isSubClassOf("TypedOperand") && in isOperandAPointer()
480 if (InstOpRec->isSubClassOf("RegisterOperand")) in tryAliasOpMatch()
[all …]
DCodeGenDAGPatterns.cpp1334 if (R->isSubClassOf("SDTCisVT")) { in SDTypeConstraint()
1340 } else if (R->isSubClassOf("SDTCisPtrTy")) { in SDTypeConstraint()
1342 } else if (R->isSubClassOf("SDTCisInt")) { in SDTypeConstraint()
1344 } else if (R->isSubClassOf("SDTCisFP")) { in SDTypeConstraint()
1346 } else if (R->isSubClassOf("SDTCisVec")) { in SDTypeConstraint()
1348 } else if (R->isSubClassOf("SDTCisSameAs")) { in SDTypeConstraint()
1351 } else if (R->isSubClassOf("SDTCisVTSmallerThanOp")) { in SDTypeConstraint()
1355 } else if (R->isSubClassOf("SDTCisOpSmallerThanOp")) { in SDTypeConstraint()
1359 } else if (R->isSubClassOf("SDTCisEltOfVec")) { in SDTypeConstraint()
1362 } else if (R->isSubClassOf("SDTCisSubVecOfVec")) { in SDTypeConstraint()
[all …]
DX86EVEX2VEXTablesEmitter.cpp164 return Rec->isSubClassOf("RegisterClass") || in isRegisterOperand()
165 Rec->isSubClassOf("RegisterOperand"); in isRegisterOperand()
169 return Rec->isSubClassOf("Operand") && in isMemoryOperand()
174 return Rec->isSubClassOf("Operand") && in isImmediateOperand()
179 if (RegRec->isSubClassOf("RegisterClass")) in getRegOperandSize()
181 if (RegRec->isSubClassOf("RegisterOperand")) in getRegOperandSize()
196 if (!Inst->TheDef->isSubClassOf("X86Inst")) in run()
DCodeGenTarget.cpp586 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
588 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
596 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && in CodeGenIntrinsic()
597 !TyEl->isSubClassOf("LLVMTruncatedType")) || in CodeGenIntrinsic()
620 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
622 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
634 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && in CodeGenIntrinsic()
635 !TyEl->isSubClassOf("LLVMTruncatedType") && in CodeGenIntrinsic()
636 !TyEl->isSubClassOf("LLVMVectorSameWidth")) || in CodeGenIntrinsic()
659 assert(Property->isSubClassOf("IntrinsicProperty") && in CodeGenIntrinsic()
[all …]
DInfoByHwMode.cpp108 if (!Rec->isSubClassOf("ValueType")) in getValueTypeByHwMode()
111 assert(Rec->isSubClassOf("ValueType") && in getValueTypeByHwMode()
113 if (Rec->isSubClassOf("HwModeSelect")) in getValueTypeByHwMode()
129 bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const { in isSubClassOf() function in RegSizeInfo
160 bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const { in isSubClassOf() function in RegSizeInfoByHwMode
162 return get(M0).isSubClassOf(I.get(M0)); in isSubClassOf()
DRISCVCompressInstEmitter.cpp133 assert(Reg->isSubClassOf("Register") && "Reg record should be a Register\n"); in validateRegister()
134 assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be" in validateRegister()
153 if (DagOpType->isSubClassOf("RegisterClass") && in validateTypes()
154 InstOpType->isSubClassOf("RegisterClass")) { in validateTypes()
161 if (DagOpType->isSubClassOf("RegisterClass") || in validateTypes()
162 InstOpType->isSubClassOf("RegisterClass")) in validateTypes()
201 if (DI->getDef()->isSubClassOf("Register")) { in addDagOperandMapping()
229 if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass")) in addDagOperandMapping()
417 if (!Operator->isSubClassOf("RVInst")) in evaluateCompressPat()
434 if (!DestOperator->isSubClassOf("RVInst16")) in evaluateCompressPat()
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DCodeGenSchedule.cpp285 if (ModelKey->isSubClassOf("SchedMachineModel")) { in addProcModel()
306 if (RWDef->isSubClassOf("WriteSequence")) { in scanSchedRW()
311 else if (RWDef->isSubClassOf("SchedVariant")) { in scanSchedRW()
340 if (RW->isSubClassOf("SchedWrite")) in collectSchedRW()
343 assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
354 if (RWDef->isSubClassOf("SchedWrite")) in collectSchedRW()
357 assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
368 if (RWDef->isSubClassOf("SchedWrite")) in collectSchedRW()
371 assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
383 if (MatchDef->isSubClassOf("SchedWrite")) { in collectSchedRW()
[all …]
DX86FoldTablesEmitter.cpp216 if (RegRec->isSubClassOf("RegisterOperand")) in getRegOperandSize()
218 if (RegRec->isSubClassOf("RegisterClass")) in getRegOperandSize()
227 if (MemRec->isSubClassOf("Operand")) { in getMemOperandSize()
279 return Rec->isSubClassOf("RegisterClass") || in isRegisterOperand()
280 Rec->isSubClassOf("RegisterOperand") || in isRegisterOperand()
281 Rec->isSubClassOf("PointerLikeRegClass"); in isRegisterOperand()
285 return Rec->isSubClassOf("Operand") && in isMemoryOperand()
290 return Rec->isSubClassOf("Operand") && in isImmediateOperand()
573 if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("X86Inst")) in run()
DIntrinsicEmitter.cpp264 if (R->isSubClassOf("LLVMMatchType")) { in EncodeFixedType()
267 if (R->isSubClassOf("LLVMExtendedType")) in EncodeFixedType()
269 else if (R->isSubClassOf("LLVMTruncatedType")) in EncodeFixedType()
271 else if (R->isSubClassOf("LLVMHalfElementsVectorType")) in EncodeFixedType()
273 else if (R->isSubClassOf("LLVMVectorSameWidth")) { in EncodeFixedType()
280 else if (R->isSubClassOf("LLVMPointerTo")) in EncodeFixedType()
282 else if (R->isSubClassOf("LLVMVectorOfAnyPointersToElt")) { in EncodeFixedType()
291 } else if (R->isSubClassOf("LLVMPointerToElt")) in EncodeFixedType()
322 if (R->isSubClassOf("LLVMQualPointerType")) { in EncodeFixedType()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCallingConvEmitter.cpp66 if (Action->isSubClassOf("CCPredicateAction")) { in EmitAction()
69 if (Action->isSubClassOf("CCIfType")) { in EmitAction()
77 } else if (Action->isSubClassOf("CCIf")) { in EmitAction()
88 if (Action->isSubClassOf("CCDelegateTo")) { in EmitAction()
93 } else if (Action->isSubClassOf("CCAssignToReg")) { in EmitAction()
114 } else if (Action->isSubClassOf("CCAssignToRegWithShadow")) { in EmitAction()
156 } else if (Action->isSubClassOf("CCAssignToStack")) { in EmitAction()
172 if (Action->isSubClassOf("CCAssignToStackWithShadow")) in EmitAction()
178 } else if (Action->isSubClassOf("CCPromoteToType")) { in EmitAction()
187 } else if (Action->isSubClassOf("CCBitConvertToType")) { in EmitAction()
[all …]
DDAGISelMatcherGen.cpp226 LeafRec->isSubClassOf("RegisterClass") || in EmitLeafMatchCode()
227 LeafRec->isSubClassOf("RegisterOperand") || in EmitLeafMatchCode()
228 LeafRec->isSubClassOf("PointerLikeRegClass") || in EmitLeafMatchCode()
229 LeafRec->isSubClassOf("SubRegIndex") || in EmitLeafMatchCode()
236 if (LeafRec->isSubClassOf("Register")) { in EmitLeafMatchCode()
243 if (LeafRec->isSubClassOf("ValueType")) in EmitLeafMatchCode()
246 if (LeafRec->isSubClassOf("CondCode")) in EmitLeafMatchCode()
249 if (LeafRec->isSubClassOf("ComplexPattern")) { in EmitLeafMatchCode()
584 if (Def->isSubClassOf("Register")) { in EmitResultLeafAsOperand()
600 if (Def->isSubClassOf("RegisterOperand")) in EmitResultLeafAsOperand()
[all …]
DCodeGenDAGPatterns.cpp747 if (!Def->isSubClassOf("Predicate")) { in getPredicateCheck()
769 if (R->isSubClassOf("SDTCisVT")) { in SDTypeConstraint()
775 } else if (R->isSubClassOf("SDTCisPtrTy")) { in SDTypeConstraint()
777 } else if (R->isSubClassOf("SDTCisInt")) { in SDTypeConstraint()
779 } else if (R->isSubClassOf("SDTCisFP")) { in SDTypeConstraint()
781 } else if (R->isSubClassOf("SDTCisVec")) { in SDTypeConstraint()
783 } else if (R->isSubClassOf("SDTCisSameAs")) { in SDTypeConstraint()
786 } else if (R->isSubClassOf("SDTCisVTSmallerThanOp")) { in SDTypeConstraint()
790 } else if (R->isSubClassOf("SDTCisOpSmallerThanOp")) { in SDTypeConstraint()
794 } else if (R->isSubClassOf("SDTCisEltOfVec")) { in SDTypeConstraint()
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DCodeGenInstruction.cpp73 if (Rec->isSubClassOf("RegisterOperand")) { in CGIOperandList()
75 } else if (Rec->isSubClassOf("Operand")) { in CGIOperandList()
94 if (Rec->isSubClassOf("PredicateOperand")) in CGIOperandList()
96 else if (Rec->isSubClassOf("OptionalDefOperand")) in CGIOperandList()
101 } else if (Rec->isSubClassOf("RegisterClass")) { in CGIOperandList()
103 } else if (!Rec->isSubClassOf("PointerLikeRegClass") && in CGIOperandList()
344 assert(FirstImplicitDef->isSubClassOf("Register")); in HasOneImplicitDefWithKnownVT()
427 if (ADI && ADI->getDef()->isSubClassOf("Register")) { in tryAliasOpMatch()
428 if (InstOpRec->isSubClassOf("OptionalDefOperand")) { in tryAliasOpMatch()
435 if (InstOpRec->isSubClassOf("RegisterOperand")) in tryAliasOpMatch()
[all …]
DCodeGenTarget.cpp408 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
410 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
418 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && in CodeGenIntrinsic()
419 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || in CodeGenIntrinsic()
442 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
444 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
452 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && in CodeGenIntrinsic()
453 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || in CodeGenIntrinsic()
476 assert(Property->isSubClassOf("IntrinsicProperty") && in CodeGenIntrinsic()
491 else if (Property->isSubClassOf("NoCapture")) { in CodeGenIntrinsic()
DInstrInfoEmitter.cpp82 if (OpR->isSubClassOf("RegisterOperand")) in GetOperandInfo()
84 if (OpR->isSubClassOf("RegisterClass")) in GetOperandInfo()
86 else if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
96 if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
101 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) in GetOperandInfo()
106 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand")) in GetOperandInfo()
DIntrinsicEmitter.cpp232 if (ArgType->isSubClassOf("LLVMMatchType")) { in EmitTypeGenerate()
235 if (ArgType->isSubClassOf("LLVMExtendedElementVectorType")) in EmitTypeGenerate()
238 else if (ArgType->isSubClassOf("LLVMTruncatedElementVectorType")) in EmitTypeGenerate()
354 if (ArgType->isSubClassOf("LLVMMatchType")) { in EmitVerifier()
359 if (ArgType->isSubClassOf("LLVMExtendedElementVectorType")) in EmitVerifier()
361 else if (ArgType->isSubClassOf("LLVMTruncatedElementVectorType")) in EmitVerifier()
382 if (ArgType->isSubClassOf("LLVMMatchType")) { in EmitVerifier()
387 if (ArgType->isSubClassOf("LLVMExtendedElementVectorType")) in EmitVerifier()
389 else if (ArgType->isSubClassOf("LLVMTruncatedElementVectorType")) in EmitVerifier()
/external/llvm/utils/TableGen/
DCallingConvEmitter.cpp85 if (Action->isSubClassOf("CCPredicateAction")) { in EmitAction()
88 if (Action->isSubClassOf("CCIfType")) { in EmitAction()
96 } else if (Action->isSubClassOf("CCIf")) { in EmitAction()
107 if (Action->isSubClassOf("CCDelegateTo")) { in EmitAction()
112 } else if (Action->isSubClassOf("CCAssignToReg")) { in EmitAction()
133 } else if (Action->isSubClassOf("CCAssignToRegWithShadow")) { in EmitAction()
174 } else if (Action->isSubClassOf("CCAssignToStack")) { in EmitAction()
198 } else if (Action->isSubClassOf("CCAssignToStackWithShadow")) { in EmitAction()
221 } else if (Action->isSubClassOf("CCPromoteToType")) { in EmitAction()
235 } else if (Action->isSubClassOf("CCPromoteToUpperBitsInType")) { in EmitAction()
[all …]
DDAGISelMatcherGen.cpp233 if (LeafRec->isSubClassOf("ValueType")) { in EmitLeafMatchCode()
242 LeafRec->isSubClassOf("RegisterClass") || in EmitLeafMatchCode()
243 LeafRec->isSubClassOf("RegisterOperand") || in EmitLeafMatchCode()
244 LeafRec->isSubClassOf("PointerLikeRegClass") || in EmitLeafMatchCode()
245 LeafRec->isSubClassOf("SubRegIndex") || in EmitLeafMatchCode()
252 if (LeafRec->isSubClassOf("Register")) { in EmitLeafMatchCode()
259 if (LeafRec->isSubClassOf("CondCode")) in EmitLeafMatchCode()
262 if (LeafRec->isSubClassOf("ComplexPattern")) { in EmitLeafMatchCode()
287 if (N->getOperator()->isSubClassOf("ComplexPattern")) { in EmitOperatorMatchCode()
617 if (Def->isSubClassOf("Register")) { in EmitResultLeafAsOperand()
[all …]
DCodeGenInstruction.cpp76 if (Rec->isSubClassOf("RegisterOperand")) { in CGIOperandList()
80 } else if (Rec->isSubClassOf("Operand")) { in CGIOperandList()
99 if (Rec->isSubClassOf("PredicateOp")) in CGIOperandList()
101 else if (Rec->isSubClassOf("OptionalDefOperand")) in CGIOperandList()
106 } else if (Rec->isSubClassOf("RegisterClass")) { in CGIOperandList()
108 } else if (!Rec->isSubClassOf("PointerLikeRegClass") && in CGIOperandList()
109 !Rec->isSubClassOf("unknown_class")) in CGIOperandList()
375 assert(FirstImplicitDef->isSubClassOf("Register")); in HasOneImplicitDefWithKnownVT()
460 if (InstOpRec->isSubClassOf("RegisterOperand")) in tryAliasOpMatch()
463 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand")) in tryAliasOpMatch()
[all …]
DCodeGenDAGPatterns.cpp876 if (!Def->isSubClassOf("Predicate")) { in getPredicateCheck()
905 if (R->isSubClassOf("SDTCisVT")) { in SDTypeConstraint()
911 } else if (R->isSubClassOf("SDTCisPtrTy")) { in SDTypeConstraint()
913 } else if (R->isSubClassOf("SDTCisInt")) { in SDTypeConstraint()
915 } else if (R->isSubClassOf("SDTCisFP")) { in SDTypeConstraint()
917 } else if (R->isSubClassOf("SDTCisVec")) { in SDTypeConstraint()
919 } else if (R->isSubClassOf("SDTCisSameAs")) { in SDTypeConstraint()
922 } else if (R->isSubClassOf("SDTCisVTSmallerThanOp")) { in SDTypeConstraint()
926 } else if (R->isSubClassOf("SDTCisOpSmallerThanOp")) { in SDTypeConstraint()
930 } else if (R->isSubClassOf("SDTCisEltOfVec")) { in SDTypeConstraint()
[all …]
DCodeGenTarget.cpp501 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
503 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
511 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && in CodeGenIntrinsic()
512 !TyEl->isSubClassOf("LLVMTruncatedType")) || in CodeGenIntrinsic()
535 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
537 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
545 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && in CodeGenIntrinsic()
546 !TyEl->isSubClassOf("LLVMTruncatedType") && in CodeGenIntrinsic()
547 !TyEl->isSubClassOf("LLVMVectorSameWidth") && in CodeGenIntrinsic()
548 !TyEl->isSubClassOf("LLVMPointerToElt")) || in CodeGenIntrinsic()
[all …]
DCodeGenSchedule.cpp164 if (ModelKey->isSubClassOf("SchedMachineModel")) { in addProcModel()
185 if (RWDef->isSubClassOf("WriteSequence")) { in scanSchedRW()
190 else if (RWDef->isSubClassOf("SchedVariant")) { in scanSchedRW()
219 if ((*RWI)->isSubClassOf("SchedWrite")) in collectSchedRW()
222 assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
234 if ((*RWI)->isSubClassOf("SchedWrite")) in collectSchedRW()
237 assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
249 if ((*RWI)->isSubClassOf("SchedWrite")) in collectSchedRW()
252 assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
264 if (MatchDef->isSubClassOf("SchedWrite")) { in collectSchedRW()
[all …]

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