Searched refs:isT2 (Results 1 – 3 of 3) sorted by relevance
1052 const TargetInstrInfo *TII, bool isT2) { in InsertLDR_STR() argument1082 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; in FixInvalidRegPairOp() local1094 bool OffKill = isT2 ? false : MI->getOperand(3).isKill(); in FixInvalidRegPairOp()1095 bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef(); in FixInvalidRegPairOp()1104 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA) in FixInvalidRegPairOp()1105 : (isT2 ? ARM::t2STMIA : ARM::STMIA); in FixInvalidRegPairOp()1127 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()1128 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()1139 Pred, PredReg, TII, isT2); in FixInvalidRegPairOp()1144 Pred, PredReg, TII, isT2); in FixInvalidRegPairOp()[all …]
1556 bool isT2) { in InsertLDR_STR() argument1597 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; in FixInvalidRegPairOp() local1607 bool OffKill = isT2 ? false : MI->getOperand(3).isKill(); in FixInvalidRegPairOp()1608 bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef(); in FixInvalidRegPairOp()1617 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA) in FixInvalidRegPairOp()1618 : (isT2 ? ARM::t2STMIA : ARM::STMIA); in FixInvalidRegPairOp()1639 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()1640 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()1644 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()1645 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()[all …]
1639 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; in FixInvalidRegPairOp() local1649 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) && in FixInvalidRegPairOp()1659 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA) in FixInvalidRegPairOp()1660 : (isT2 ? ARM::t2STMIA : ARM::STMIA); in FixInvalidRegPairOp()1681 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()1682 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()1686 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()1687 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()2022 bool &isT2);2101 bool &isT2) { in CanFormLdStDWord() argument[all …]