Searched refs:isThumb1 (Results 1 – 9 of 9) sorted by relevance
114 bool isThumb1, isThumb2; member486 assert(isThumb1 && "Can only update base register uses for Thumb1!"); in UpdateBaseRegUses()632 bool SafeToClobberCPSR = !isThumb1 || in CreateLoadStoreMulti()636 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback. in CreateLoadStoreMulti()641 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()652 bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1; in CreateLoadStoreMulti()658 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) { in CreateLoadStoreMulti()692 NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass); in CreateLoadStoreMulti()699 (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi : in CreateLoadStoreMulti()700 (isThumb1 && Offset < 8) ? ARM::tADDi3 : in CreateLoadStoreMulti()[all …]
217 bool isThumb1; member in __anonfed5db4b0111::ARMConstantIslands355 isThumb1 = AFI->isThumb1OnlyFunction(); in runOnMachineFunction()359 bool GenerateTBB = isThumb2 || (isThumb1 && SynthesizeThumb1TBB); in runOnMachineFunction()651 return isThumb1 ? 2 : 0; in getCPELogAlign()653 return isThumb1 ? 2 : 1; in getCPELogAlign()1308 unsigned Delta = isThumb1 ? 2 : 4; in createNewWater()1632 if (!isThumb1) in fixupUnconditionalBr()
1396 bool isThumb1 = Subtarget.isThumb1Only(); in expandMEMCPY() local1404 if (isThumb1 || !MI->getOperand(1).isDead()) { in expandMEMCPY()1407 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()1414 if (isThumb1 || !MI->getOperand(0).isDead()) { in expandMEMCPY()1417 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
9533 bool isThumb1 = Subtarget->isThumb1Only(); in attachMEMCPYScratchRegs() local9550 unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass in attachMEMCPYScratchRegs()
98 bool isThumb1, isThumb2; member461 assert(isThumb1 && "Can only update base register uses for Thumb1!"); in UpdateBaseRegUses()603 bool SafeToClobberCPSR = !isThumb1 || in CreateLoadStoreMulti()607 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback. in CreateLoadStoreMulti()612 if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()624 bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1; in CreateLoadStoreMulti()630 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) { in CreateLoadStoreMulti()664 NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass); in CreateLoadStoreMulti()671 (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi : in CreateLoadStoreMulti()672 (isThumb1 && Offset < 8) ? ARM::tADDi3 : in CreateLoadStoreMulti()[all …]
274 bool isThumb1; member in __anon8e1325130111::ARMConstantIslands411 isThumb1 = AFI->isThumb1OnlyFunction(); in runOnMachineFunction()1381 unsigned Delta = isThumb1 ? 2 : 4; in createNewWater()1696 if (!isThumb1) in fixupUnconditionalBr()
1231 bool isThumb1 = Subtarget.isThumb1Only(); in expandMEMCPY() local1239 if (isThumb1 || !MI->getOperand(1).isDead()) { in expandMEMCPY()1241 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()1248 if (isThumb1 || !MI->getOperand(0).isDead()) { in expandMEMCPY()1250 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
8490 bool isThumb1 = Subtarget->isThumb1Only(); in attachMEMCPYScratchRegs() local8507 unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass in attachMEMCPYScratchRegs()
172 bool isThumb1; member in __anona28af83f0111::ARMConstantIslands280 isThumb1 = AFI->isThumb1OnlyFunction(); in runOnMachineFunction()306 if (!isThumb1) in runOnMachineFunction()314 if (isThumb1) in runOnMachineFunction()793 int delta = isThumb1 ? 2 : 4; in SplitBlockBeforeInstr()1146 OffsetIsInRange(UserOffset, OffsetOfNextBlock + (isThumb1 ? 2: 4), in CreateNewWater()1166 int delta = isThumb1 ? 2 : 4; in CreateNewWater()1193 (isThumb1 ? 6 : 8); in CreateNewWater()1209 BaseInsertOffset -= (isThumb1 ? 2 : 4); in CreateNewWater()1210 EndInsertOffset -= (isThumb1 ? 2 : 4); in CreateNewWater()[all …]