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Searched refs:kSRegSize (Results 1 – 18 of 18) sorted by relevance

/external/vixl/src/aarch64/
Dlogic-aarch64.cc2277 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcadd()
2403 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmla()
2420 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmla()
4175 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { \
4219 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in frecps()
4251 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in frsqrts()
4308 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmp()
4327 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmp_zero()
4349 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fabscmp()
4386 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fmla()
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Doperands-aarch64.h151 (size_ == kSRegSize) || (size_ == kDRegSize) || in IsValidVRegister()
367 VRegister V2H() const { return VRegister(code_, kSRegSize, 2); } in V2H()
407 bool IsLaneSizeS() const { return GetLaneSizeInBits() == kSRegSize; } in IsLaneSizeS()
466 const VRegister s##N(N, kSRegSize); \
Dinstructions-aarch64.h67 const unsigned kSRegSize = 32; variable
69 const unsigned kSRegSizeInBytes = kSRegSize / 8;
Dinstructions-aarch64.cc552 return kSRegSize; in RegisterSizeInBitsFromFormat()
Dmacro-assembler-aarch64.h860 PushSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PushSRegList()
863 PopSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PopSRegList()
930 PeekSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PeekSRegList()
933 PokeSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PokeSRegList()
Ddisasm-aarch64.cc4739 case kSRegSize: in AppendRegisterNameToOutput()
5057 reg_size = kSRegSize; in SubstituteRegisterField()
Dsimulator-aarch64.h1063 case kSRegSize:
Dassembler-aarch64.cc5800 case kSRegSize: in LoadOpFor()
5823 case kSRegSize: in StoreOpFor()
/external/v8/src/arm64/
Dsimulator-logic-arm64.cc3285 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { \
3321 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frecps()
3347 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frsqrts()
3395 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp()
3407 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp_zero()
3424 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabscmp()
3455 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmla()
3482 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmls()
3505 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fneg()
3530 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabs_()
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Ddeoptimizer-arm64.cc125 (saved_float_registers.Count() * kSRegSize); in Generate()
130 kFloatRegistersOffset + saved_float_registers.Count() * kSRegSize; in Generate()
Dsimulator-arm64.h884 (sizeof(T) == kSRegSize) || (sizeof(T) == kDRegSize) || in vreg()
925 case kSRegSize: in vreg()
948 (sizeof(value) == kSRegSize) || (sizeof(value) == kDRegSize) ||
1000 (sizeof(value) == kSRegSize) || in set_vreg_no_log()
1165 static_assert(sizeof(value) == kSRegSize, in GetPrintRegisterFormat()
1186 case kSRegSize: in GetPrintRegisterFormatForSizeFP()
1192 if ((GetPrintRegLaneSizeInBytes(format) == kSRegSize) || in GetPrintRegisterFormatTryFP()
Dinstructions-arm64.cc176 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size."); in CalcLSPairDataSize()
Dsimulator-arm64.cc952 case kSRegSize: in GetPrintRegisterFormatForSize()
965 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size."); in GetPrintRegisterFormatForSize()
1191 DCHECK((lane_size_in_bytes == kSRegSize) || in PrintVRegisterFPHelper()
1204 const char* name = (lane_size_in_bytes == kSRegSize) in PrintVRegisterFPHelper()
1220 double value = (lane_size_in_bytes == kSRegSize) in PrintVRegisterFPHelper()
1908 DCHECK_EQ(access_size, static_cast<unsigned>(kSRegSize)); in LoadStorePairHelper()
1944 DCHECK_EQ(access_size, static_cast<unsigned>(kSRegSize)); in LoadStorePairHelper()
Dconstants-arm64.h56 const int kSRegSize = kSRegSizeInBits >> 3; variable
/external/vixl/examples/aarch64/
Dneon-matrix-multiply.cc49 VRegister v_in = VRegister(in_column, kSRegSize); in GenerateMultiplyColumn()
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc249 VIXL_ASSERT((d_size == kDRegSize) || (d_size == kSRegSize) || in Test1Op_Helper()
251 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize) || in Test1Op_Helper()
271 } else if (n_size == kSRegSize) { in Test1Op_Helper()
281 } else if (d_size == kSRegSize) { in Test1Op_Helper()
391 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize) || in Test2Op_Helper()
407 bool float_op = reg_size == kSRegSize; in Test2Op_Helper()
549 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize) || in Test3Op_Helper()
566 bool single_op = reg_size == kSRegSize; in Test3Op_Helper()
708 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmp_Helper()
850 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmpZero_Helper()
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Dtest-utils-aarch64.cc366 s[i] = FPRegister(n, kSRegSize); in PopulateFPRegisterArray()
Dtest-assembler-aarch64.cc15647 ASSERT_EQUAL_FP64(RawbitsToDouble((base_d >> kSRegSize) | in TEST()
15648 ((2 * base_d) << kSRegSize)), in TEST()
15652 ASSERT_EQUAL_FP32(RawbitsToFloat((4 * base_d) >> kSRegSize), s17); in TEST()
15747 VIXL_CHECK(array[12] == ((1 * low_base) << kSRegSize)); in TEST()
15748 VIXL_CHECK(array[13] == (((2 * low_base) << kSRegSize) | (1 * high_base))); in TEST()
15749 VIXL_CHECK(array[14] == (((3 * low_base) << kSRegSize) | (2 * high_base))); in TEST()
15750 VIXL_CHECK(array[15] == (((4 * low_base) << kSRegSize) | (3 * high_base))); in TEST()
15751 VIXL_CHECK(array[16] == (((1 * low_base) << kSRegSize) | (4 * high_base))); in TEST()
15752 VIXL_CHECK(array[17] == (((2 * low_base) << kSRegSize) | (1 * high_base))); in TEST()
15753 VIXL_CHECK(array[18] == (((3 * low_base) << kSRegSize) | (2 * high_base))); in TEST()
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