Searched refs:lcd0_ch0_clk_cfg (Results 1 – 4 of 4) sorted by relevance
70 u32 lcd0_ch0_clk_cfg; /* 0x118 */ member
83 u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ member
308 &ccm->lcd0_ch0_clk_cfg); in lcdc_pll_set()
530 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST); in sunxi_lcdc_init()823 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);