| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 3 ldaexb r3, [r4]
8 @ CHECK: ldaexb r3, [r4] @ encoding: [0x9f,0x3e,0xd4,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 3 ldaexb r3, [r4]
8 @ CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f]
|
| D | thumbv8m.s | 121 ldaexb r1, [r2] label
|
| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 3 ldaexb r3, [r4]
8 @ CHECK: ldaexb r3, [r4] @ encoding: [0x9f,0x3e,0xd4,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 3 ldaexb r3, [r4]
8 @ CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f]
|
| D | thumbv8m.s | 121 ldaexb r1, [r2] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s.cs | 2 0xd4,0xe8,0xcf,0x3f = ldaexb r3, [r4]
|
| D | load-store-acquire-release-v8.s.cs | 2 0x9f,0x3e,0xd4,0xe1 = ldaexb r3, [r4]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 7 # CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f]
|
| D | load-store-acquire-release-v8.txt | 6 # CHECK: ldaexb r0, [r8] @ encoding: [0x9f,0x0e,0xd8,0xe1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 7 # CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f]
|
| D | load-store-acquire-release-v8.txt | 6 # CHECK: ldaexb r0, [r8] @ encoding: [0x9f,0x0e,0xd8,0xe1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 35 ; CHECK: ldaexb r0, [r0]
|
| D | atomic-ops-v8.ll | 20 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
308 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
404 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
589 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
702 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
928 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
1043 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 35 ; CHECK: ldaexb r0, [r0]
|
| D | atomic-ops-v8.ll | 20 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
308 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
404 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
589 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
702 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
928 ; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
1043 ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2284 void ldaexb(Condition cond, Register rt, const MemOperand& operand);
2285 void ldaexb(Register rt, const MemOperand& operand) { in ldaexb() function
2286 ldaexb(al, rt, operand); in ldaexb()
|
| D | disasm-aarch32.h | 777 void ldaexb(Condition cond, Register rt, const MemOperand& operand);
|
| D | disasm-aarch32.cc | 1596 void Disassembler::ldaexb(Condition cond, in ldaexb() function in vixl::aarch32::Disassembler
10515 ldaexb(CurrentCond(), in DecodeT32()
60255 ldaexb(condition, in DecodeA32()
|
| D | assembler-aarch32.cc | 4663 void Assembler::ldaexb(Condition cond, Register rt, const MemOperand& operand) { in ldaexb() function in vixl::aarch32::Assembler
4686 Delegate(kLdaexb, &Assembler::ldaexb, cond, rt, operand); in ldaexb()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3295 "ldaexb", "\t$Rt, $addr", "",
|
| D | ARMInstrInfo.td | 4964 NoItinerary, "ldaexb", "\t$Rt, $addr",
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3313 "ldaexb", "\t$Rt, $addr", "",
|
| D | ARMInstrInfo.td | 4699 NoItinerary, "ldaexb", "\t$Rt, $addr",
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7741 "ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ldc2\005l"
8133 …{ 379 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|F…
8134 …{ 379 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Featu…
|