| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 4 ldaexh r2, [r5]
9 @ CHECK: ldaexh r2, [r5] @ encoding: [0x9f,0x2e,0xf5,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 4 ldaexh r2, [r5]
9 @ CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f]
|
| D | thumbv8m.s | 124 ldaexh r1, [r2] label
|
| /external/llvm/test/MC/ARM/ |
| D | load-store-acquire-release-v8.s | 4 ldaexh r2, [r5]
9 @ CHECK: ldaexh r2, [r5] @ encoding: [0x9f,0x2e,0xf5,0xe1]
|
| D | load-store-acquire-release-v8-thumb.s | 4 ldaexh r2, [r5]
9 @ CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f]
|
| D | thumbv8m.s | 124 ldaexh r1, [r2] label
|
| /external/capstone/suite/MC/ARM/ |
| D | load-store-acquire-release-v8-thumb.s.cs | 3 0xd5,0xe8,0xdf,0x2f = ldaexh r2, [r5]
|
| D | load-store-acquire-release-v8.s.cs | 3 0x9f,0x2e,0xf5,0xe1 = ldaexh r2, [r5]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 8 # CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f]
|
| D | load-store-acquire-release-v8.txt | 7 # CHECK: ldaexh r1, [r12] @ encoding: [0x9f,0x1e,0xfc,0xe1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | load-store-acquire-release-v8-thumb.txt | 8 # CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f]
|
| D | load-store-acquire-release-v8.txt | 7 # CHECK: ldaexh r1, [r12] @ encoding: [0x9f,0x1e,0xfc,0xe1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 45 ; CHECK: ldaexh r0, [r0]
|
| D | atomic-ops-v8.ll | 43 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
522 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
728 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
841 ; CHECK: ldaexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
1077 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | ldaex-stlex.ll | 45 ; CHECK: ldaexh r0, [r0]
|
| D | atomic-ops-v8.ll | 43 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
522 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
728 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
841 ; CHECK: ldaexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
1076 ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2297 void ldaexh(Condition cond, Register rt, const MemOperand& operand);
2298 void ldaexh(Register rt, const MemOperand& operand) { in ldaexh() function
2299 ldaexh(al, rt, operand); in ldaexh()
|
| D | disasm-aarch32.h | 784 void ldaexh(Condition cond, Register rt, const MemOperand& operand);
|
| D | disasm-aarch32.cc | 1614 void Disassembler::ldaexh(Condition cond, in ldaexh() function in vixl::aarch32::Disassembler
10528 ldaexh(CurrentCond(), in DecodeT32()
60318 ldaexh(condition, in DecodeA32()
|
| D | assembler-aarch32.cc | 4721 void Assembler::ldaexh(Condition cond, Register rt, const MemOperand& operand) { in ldaexh() function in vixl::aarch32::Assembler
4744 Delegate(kLdaexh, &Assembler::ldaexh, cond, rt, operand); in ldaexh()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3300 "ldaexh", "\t$Rt, $addr", "",
|
| D | ARMInstrInfo.td | 4967 NoItinerary, "ldaexh", "\t$Rt, $addr",
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3318 "ldaexh", "\t$Rt, $addr", "",
|
| D | ARMInstrInfo.td | 4702 NoItinerary, "ldaexh", "\t$Rt, $addr",
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7741 "ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ldc2\005l"
8137 …{ 393 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|F…
8138 …{ 393 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Featu…
|