| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | arm-load-store-multiple-deprecated.s | 187 .global ldmib symbol
188 .type ldmib,%function
189 ldmib: label
190 ldmib r0!, {r1, sp}
192 ldmib r0!, {sp}
194 ldmib r0!, {r1, lr, pc}
196 ldmib r0!, {lr, pc}
|
| D | basic-arm-instructions.s | 1162 ldmib r2, {r1,r3-r6,sp}
1169 ldmib r2!, {r1,r3-r6,sp}
1179 @ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
1185 @ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
|
| /external/llvm/test/MC/ARM/ |
| D | arm-load-store-multiple-deprecated.s | 187 .global ldmib symbol
188 .type ldmib,%function
189 ldmib: label
190 ldmib r0!, {r1, sp}
192 ldmib r0!, {sp}
194 ldmib r0!, {r1, lr, pc}
196 ldmib r0!, {lr, pc}
|
| D | basic-arm-instructions.s | 1160 ldmib r2, {r1,r3-r6,sp}
1167 ldmib r2!, {r1,r3-r6,sp}
1177 @ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
1183 @ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | ldm.ll | 31 ; CHECK: ldmib
34 ; V4T: ldmib
|
| /external/llvm/test/CodeGen/ARM/ |
| D | ldm.ll | 31 ; CHECK: ldmib
34 ; V4T: ldmib
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | ldm.ll | 31 ; CHECK: ldmib
34 ; V4T: ldmib
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 318 0x7a,0x20,0x92,0xe9 = ldmib r2, {r1, r3, r4, r5, r6, sp}
323 0x7a,0x20,0xb2,0xe9 = ldmib r2!, {r1, r3, r4, r5, r6, sp}
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 736 ldmib r2, {r1,r3-r6,sp}
743 ldmib r2!, {r1,r3-r6,sp}
749 @ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
755 @ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 585 # CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp}
591 # CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp}
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 666 # CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp}
672 # CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp}
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 666 # CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp}
672 # CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp}
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2387 void ldmib(Condition cond,
2391 void ldmib(Register rn, WriteBack write_back, RegisterList registers) { in ldmib() function
2392 ldmib(al, rn, write_back, registers); in ldmib()
|
| D | disasm-aarch32.h | 825 void ldmib(Condition cond,
|
| D | assembler-aarch32.cc | 4977 void Assembler::ldmib(Condition cond, in ldmib() function in vixl::aarch32::Assembler
4992 Delegate(kLdmib, &Assembler::ldmib, cond, rn, write_back, registers); in ldmib()
|
| D | macro-assembler-aarch32.h | 2063 ldmib(cond, rn, write_back, registers); in Ldmib()
|
| D | disasm-aarch32.cc | 1695 void Disassembler::ldmib(Condition cond, in ldmib() function in vixl::aarch32::Disassembler
64670 ldmib(condition, Register(rn), write_back, registers); in DecodeA32()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7742 "dc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005ldrbt\004"
8195 …{ 441 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_Cond…
8196 …{ 441 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsA…
8197 …{ 441 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_C…
8198 …{ 441 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_…
|