/external/llvm/test/MC/AArch64/ |
D | arm64-memory.s | 118 ldursb w9, [x3] 119 ldursb x2, [sp, #128] 133 ; CHECK: ldursb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x38] 134 ; CHECK: ldursb x2, [sp, #128] ; encoding: [0xe2,0x03,0x88,0x38] 619 ; CHECK: ldursb w6, [x4, #-1] ; encoding: [0x86,0xf0,0xdf,0x38] 620 ; CHECK: ldursb x7, [x5, #-1] ; encoding: [0xa7,0xf0,0x9f,0x38]
|
D | basic-a64-diagnostics.s | 1917 ldursb x9, [sp, #-257]
|
D | basic-a64-instructions.s | 2356 ldursb x9, [x7, #-256] 2361 ldursb w19, [x1, #-256]
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
D | arm64-memory.s | 118 ldursb w9, [x3] 119 ldursb x2, [sp, #128] 133 ; CHECK: ldursb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x38] 134 ; CHECK: ldursb x2, [sp, #128] ; encoding: [0xe2,0x03,0x88,0x38] 619 ; CHECK: ldursb w6, [x4, #-1] ; encoding: [0x86,0xf0,0xdf,0x38] 620 ; CHECK: ldursb x7, [x5, #-1] ; encoding: [0xa7,0xf0,0x9f,0x38]
|
D | basic-a64-diagnostics.s | 1948 ldursb x9, [sp, #-257]
|
D | basic-a64-instructions.s | 2339 ldursb x9, [x7, #-256] 2344 ldursb w19, [x1, #-256]
|
/external/llvm/test/CodeGen/AArch64/ |
D | ldst-unscaledimm.ll | 26 ; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] 47 ; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
|
D | fast-isel-int-ext2.ll | 80 ; CHECK: ldursb w0, [x0, #-8] 108 ; CHECK: ldursb x0, [x0, #-8]
|
D | fast-isel-int-ext.ll | 207 ; CHECK: ldursb w0, [x0, #-8] 229 ; CHECK: ldursb x0, [x0, #-8]
|
D | arm64-scvt.ll | 657 ; CHECK-A57: ldursb w[[REGNUM:[0-9]+]], [x0, #-1] 718 ; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1] 784 ; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | ldst-unscaledimm.ll | 26 ; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] 47 ; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
|
D | fast-isel-int-ext2.ll | 80 ; CHECK: ldursb w0, [x0, #-8] 108 ; CHECK: ldursb x0, [x0, #-8]
|
D | fast-isel-int-ext.ll | 207 ; CHECK: ldursb w0, [x0, #-8] 229 ; CHECK: ldursb x0, [x0, #-8]
|
D | arm64-scvt.ll | 657 ; CHECK-A57: ldursb w[[REGNUM:[0-9]+]], [x0, #-1] 718 ; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1] 784 ; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-memory.txt | 131 # CHECK: ldursb w9, [x3] 132 # CHECK: ldursb x2, [sp, #128]
|
D | basic-a64-instructions.txt | 2021 # CHECK: ldursb x9, [x7, #-256] 2025 # CHECK: ldursb w19, [x1, #-256]
|
/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-memory.txt | 131 # CHECK: ldursb w9, [x3] 132 # CHECK: ldursb x2, [sp, #128]
|
D | basic-a64-instructions.txt | 2037 # CHECK: ldursb x9, [x7, #-256] 2041 # CHECK: ldursb w19, [x1, #-256]
|
/external/capstone/suite/MC/AArch64/ |
D | basic-a64-instructions.s.cs | 917 0xe9,0x00,0x90,0x38 = ldursb x9, [x7, #-256] 922 0x33,0x00,0xd0,0x38 = ldursb w19, [x1, #-256]
|
/external/vixl/test/aarch64/ |
D | test-disasm-aarch64.cc | 1532 COMPARE(ldursb(w0, MemOperand(x1)), "ldursb w0, [x1]"); in TEST() 1533 COMPARE(ldursb(w2, MemOperand(x3, 1)), "ldursb w2, [x3, #1]"); in TEST() 1534 COMPARE(ldursb(x2, MemOperand(x3, 255)), "ldursb x2, [x3, #255]"); in TEST() 1624 COMPARE(ldursb(w0, MemOperand(x1), option), "ldursb w0, [x1]"); in TEST() 1625 COMPARE(ldursb(w2, MemOperand(x3, 1), option), "ldursb w2, [x3, #1]"); in TEST() 1626 COMPARE(ldursb(x2, MemOperand(x3, 255), option), "ldursb x2, [x3, #255]"); in TEST()
|
D | test-trace-aarch64.cc | 215 __ ldursb(w18, MemOperand(x0, 1)); in GenerateTestSequenceBase() local 216 __ ldursb(x19, MemOperand(x0, 1)); in GenerateTestSequenceBase() local
|
/external/vixl/src/aarch64/ |
D | assembler-aarch64.h | 1264 void ldursb(const Register& rt,
|
/external/vixl/test/test-trace-reference/ |
D | log-disasm | 162 0x~~~~~~~~~~~~~~~~ 38c01012 ldursb w18, [x0, #1] 163 0x~~~~~~~~~~~~~~~~ 38801013 ldursb x19, [x0, #1]
|
D | log-disasm-colour | 162 0x~~~~~~~~~~~~~~~~ 38c01012 ldursb w18, [x0, #1] 163 0x~~~~~~~~~~~~~~~~ 38801013 ldursb x19, [x0, #1]
|
/external/vixl/doc/aarch64/ |
D | supported-instructions-aarch64.md | 684 void ldursb(const Register& rt,
|