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Searched refs:lis (Results 1 – 25 of 208) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DSplitter.cpp45 StartSlotComparator(LiveIntervals &lis) : lis(lis) {} in StartSlotComparator() argument
48 return lis.getMBBStartIdx(mbb1) < lis.getMBBStartIdx(mbb2); in operator ()()
51 LiveIntervals &lis; member in llvm::StartSlotComparator
101 newLI = &ls.lis->getOrCreateInterval(vreg); in getNewLI()
111 ls.lis->getVNInfoAllocator()); in getNewVNI()
131 ls.lis->findExitingRange(li, preHeader); in applyIncoming()
142 ls.lis->InsertMachineInstrInMaps(copy); in applyIncoming()
144 SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getDefIndex(); in applyIncoming()
149 li.removeRange(copyDefIdx, ls.lis->getMBBEndIdx(preHeader), true); in applyIncoming()
152 ls.lis->getMBBEndIdx(preHeader), in applyIncoming()
[all …]
DLiveRangeEdit.cpp56 void LiveRangeEdit::scanRemattable(LiveIntervals &lis, in scanRemattable() argument
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def); in scanRemattable()
72 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis, in anyRematerializable() argument
76 scanRemattable(lis, tii, aa); in anyRematerializable()
85 LiveIntervals &lis) { in allUsesAvailableAt() argument
93 if (MO.isUndef() || !lis.hasInterval(MO.getReg())) in allUsesAvailableAt()
101 LiveInterval &li = lis.getInterval(MO.getReg()); in allUsesAvailableAt()
114 LiveIntervals &lis) { in canRematerializeAt() argument
124 DefIdx = lis.getInstructionIndex(RM.OrigMI); in canRematerializeAt()
127 RM.OrigMI = lis.getInstructionFromIndex(DefIdx); in canRematerializeAt()
[all …]
DRegAllocPBQP.cpp135 LiveIntervals *lis; member in __anonaf47a6de0111::RegAllocPBQP
193 const LiveIntervals *lis, in build() argument
207 for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end(); in build()
222 const LiveInterval *vregLI = &lis->getInterval(vreg); in build()
240 const LiveInterval *pregLI = &lis->getInterval(preg); in build()
288 const LiveInterval &l1 = lis->getInterval(vr1); in build()
294 const LiveInterval &l2 = lis->getInterval(vr2); in build()
339 const LiveIntervals *lis, in build() argument
343 std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs); in build()
380 if (!lis->isAllocatable(dst)) { in build()
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DSpiller.cpp56 LiveIntervals *lis; member in __anon475fb45d0211::SpillerBase
66 lis = &pass.getAnalysis<LiveIntervals>(); in SpillerBase()
122 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg); in trivialSpillEverywhere()
143 lis->InsertMachineInstrInMaps(loadInstr).getDefIndex(); in trivialSpillEverywhere()
147 newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator()); in trivialSpillEverywhere()
157 lis->InsertMachineInstrInMaps(storeInstr).getDefIndex(); in trivialSpillEverywhere()
161 newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator()); in trivialSpillEverywhere()
197 LiveIntervals *lis; member in __anon475fb45d0411::StandardSpiller
205 lis(&pass.getAnalysis<LiveIntervals>()), in StandardSpiller()
213 lis->addIntervalsForSpills(LRE.getParent(), LRE.getUselessVRegs(), in spill()
DRenderMachineFunction.cpp196 LiveIntervals *lis, in setup() argument
200 this->lis = lis; in setup()
269 for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end(); in translateIntervalNumbersToCurrentFunction()
296 if (lis->hasInterval(reg)) { in translateIntervalNumbersToCurrentFunction()
297 intervalSet.insert(&lis->getInterval(reg)); in translateIntervalNumbersToCurrentFunction()
316 LiveIntervals *lis) { in setup() argument
320 this->lis = lis; in setup()
460 for (LiveIntervals::iterator liItr = lis->begin(), in resetPressureAndLiveStates()
461 liEnd = lis->end(); in resetPressureAndLiveStates()
922 lis = &getAnalysis<LiveIntervals>(); in runOnMachineFunction()
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DCalcSpillWeights.cpp48 LiveIntervals &lis = getAnalysis<LiveIntervals>(); in runOnMachineFunction() local
49 VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>()); in runOnMachineFunction()
50 for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) { in runOnMachineFunction()
DRenderMachineFunction.h63 LiveIntervals *lis, const RenderMachineFunction *rmf);
119 LiveIntervals *lis; variable
142 const TargetRegisterInfo *tri, LiveIntervals *lis);
171 LiveIntervals *lis; variable
248 LiveIntervals *lis; variable
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dstart.S135 lis r2, L2CSR0_L2E@h
142 lis r2,(L2CSR0_L2FL)@h
155 lis r2, L2CSR0_L2E@h
178 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
181 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
184 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
187 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
190 lis \scratch, \phy_high@h
200 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
203 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
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Drelease.S37 lis r3, HID0_EMCP@h /* enable machine check */
92 lis r3,BUCSR_ENABLE@h
102 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
110 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
120 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
128 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
140 lis r3,toreset(__spin_table_addr)@h
216 lis r5,SVR_P4080@h
227 lis r3,toreset(enable_cpu_a011_workaround)@ha
258 lis r3,SVR_P2040@h
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/external/u-boot/arch/powerpc/cpu/mpc86xx/
Dstart.S159 lis r3, L2_INIT@h
170 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
199 lis r3,addr_trans_enabled@h
226 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
242 lis r4, PIXIS_BASE@h
260 lis r3, CONFIG_SYS_DIAG_ADDR@h
310 lis r4, CONFIG_SYS_IBAT##n##L@h; \
312 lis r3, CONFIG_SYS_IBAT##n##U@h; \
316 lis r4, CONFIG_SYS_DBAT##n##L@h; \
318 lis r3, CONFIG_SYS_DBAT##n##U@h; \
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/external/llvm/test/CodeGen/PowerPC/
Dpr26356.ll8 ; CHECK: lis 3, 0
16 ; CHECK: lis 3, 0
31 ; CHECK: lis 3, 0
39 ; CHECK: lis 3, 0
54 ; CHECK: lis 3, 0
62 ; CHECK: lis 3, 0
70 ; CHECK: lis 3, 0
78 ; CHECK: lis 3, 0
100 ; CHECK: lis 3, -1
122 ; CHECK: lis 3, -1
Dconstants-i64.ll11 ; CHECK: lis [[REG1:[0-9]+]], -1
22 ; CHECK: lis [[REG1:[0-9]+]], -81
55 ; CHECK: lis [[REG1:[0-9]+]], -4096
66 ; CHECK: lis [[REG1:[0-9]+]], -32768
77 ; CHECK: lis [[REG1:[0-9]+]], -5121
D2010-02-12-saveCR.ll10 ; CHECK: lis [[T2:r[0-9]+]], 1
15 ; CHECK: lis [[T3:r[0-9]+]], 1
28 ; CHECK: lis [[T1:r[0-9]+]], 1
33 ; CHECK: lis [[T1]], 1
DFrames-large.ll16 ; PPC32-NOFP: lis r0, -1
25 ; PPC32-FP: lis r0, -1
37 ; PPC64-NOFP: lis r0, -1
46 ; PPC64-FP: lis r0, -1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
DtestBitReverse.ll8 ; CHECK-NEXT: lis 4, -21846
9 ; CHECK-NEXT: lis 5, 21845
16 ; CHECK-NEXT: lis 5, 13107
18 ; CHECK-NEXT: lis 4, -13108
25 ; CHECK-NEXT: lis 5, 3855
27 ; CHECK-NEXT: lis 4, -3856
48 ; CHECK-NEXT: lis 4, -21846
49 ; CHECK-NEXT: lis 5, 21845
50 ; CHECK-NEXT: lis 6, -13108
51 ; CHECK-NEXT: lis 7, 13107
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Dpr26356.ll8 ; CHECK: lis 3, 0
16 ; CHECK: lis 3, 0
31 ; CHECK: lis 3, 0
39 ; CHECK: lis 3, 0
54 ; CHECK: lis 3, 0
62 ; CHECK: lis 3, 0
70 ; CHECK: lis 3, 0
78 ; CHECK: lis 3, 0
100 ; CHECK: lis 3, -1
122 ; CHECK: lis 3, -1
Dpr33093.ll8 ; CHECK-NEXT: lis 4, -21846
9 ; CHECK-NEXT: lis 5, 21845
16 ; CHECK-NEXT: lis 5, 13107
18 ; CHECK-NEXT: lis 4, -13108
25 ; CHECK-NEXT: lis 5, 3855
27 ; CHECK-NEXT: lis 4, -3856
72 ; CHECK-NEXT: lis 4, -21846
73 ; CHECK-NEXT: lis 5, 21845
74 ; CHECK-NEXT: lis 6, -13108
75 ; CHECK-NEXT: lis 7, 13107
[all …]
Dconstants-i64.ll11 ; CHECK: lis [[REG1:[0-9]+]], -1
22 ; CHECK: lis [[REG1:[0-9]+]], -81
55 ; CHECK: lis [[REG1:[0-9]+]], -4096
66 ; CHECK: lis [[REG1:[0-9]+]], -32768
77 ; CHECK: lis [[REG1:[0-9]+]], -5121
D2010-02-12-saveCR.ll10 ; CHECK: lis [[T2:r[0-9]+]], 1
15 ; CHECK: lis [[T3:r[0-9]+]], 1
28 ; CHECK: lis [[T1:r[0-9]+]], 1
33 ; CHECK: lis [[T1]], 1
D2008-10-28-f128-i32.ll13 ; CHECK-NEXT: lis 3, .LCPI0_0@ha
44 ; CHECK-NEXT: lis 3, 15856
66 ; CHECK-NEXT: lis 3, 16864
90 ; CHECK-NEXT: lis 3, .LCPI0_1@ha
121 ; CHECK-NEXT: lis 3, 17392
189 ; CHECK-NEXT: lis 3, 16864
211 ; CHECK-NEXT: lis 3, .LCPI0_2@ha
220 ; CHECK-NEXT: lis 3, .LCPI0_3@ha
244 ; CHECK-NEXT: lis 4, 16864
266 ; CHECK-NEXT: lis 3, .LCPI0_0@ha
[all …]
DFrames-large.ll13 ; PPC32-NOFP: lis r0, -1
22 ; PPC32-FP: lis r0, -1
34 ; PPC64-NOFP: lis r0, -1
43 ; PPC64-FP: lis r0, -1
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dstart.S164 lis r4, CONFIG_DEFAULT_IMMR@h
173 lis r3, CONFIG_SYS_IMMR@h
209 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
252 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
293 lis r3, CONFIG_SYS_IMMR@h
429 lis r22,MSR_POW@h
501 lis r3, CONFIG_SYS_IMMR@h
505 lis r4, CONFIG_SYS_WATCHDOG_VALUE
544 lis r3, CONFIG_SYS_HID0_INIT@h
549 lis r3, CONFIG_SYS_HID0_FINAL@h
[all …]
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dstart.S72 lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
97 lis r3, IDC_UNALL@h /* Unlock all */
101 lis r3, IDC_INVALL@h /* Invalidate all */
105 lis r3, IDC_DISABLE@h /* Disable data cache */
108 lis r3, IDC_ENABLE@h /* Enable instruction cache */
121 lis r3, CONFIG_SYS_MONITOR_BASE@h
143 lis r2, CONFIG_SYS_DER@h
148 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
156 lis r4, CONFIG_SYS_IMMR@h
173 lis r3, CONFIG_SYS_IMMR@h
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
DFrames-large.ll17 ; PPC32-NOFP: lis r0, -1
26 ; PPC32-FP: lis r0, -1
36 ; PPC64-NOFP: lis r0, -1
46 ; PPC64-FP: lis r0, -1
/external/syzkaller/vendor/google.golang.org/grpc/
Dserver.go94 lis map[net.Listener]bool member
346 lis: make(map[net.Listener]bool),
503 func (s *Server) Serve(lis net.Listener) error {
507 if s.lis == nil {
510 lis.Close()
525 ls := &listenSocket{Listener: lis}
526 s.lis[ls] = true
535 if s.lis != nil && s.lis[ls] {
537 delete(s.lis, ls)
545 rawConn, err := lis.Accept()
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