Searched refs:masking (Results 1 – 25 of 105) sorted by relevance
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Lanai/ |
| D | masking_setccs.ll | 3 ; Test that unnecessary masking with 0x1 is not inserted.
8 ; CHECK-LABEL: masking:
10 define i32 @masking(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
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| /external/llvm/test/MC/Mips/ |
| D | nacl-mask.s | 4 # This test tests that address-masking sandboxing is added when given assembly
8 # Test that address-masking sandboxing is added before indirect branches and
36 # Test that address-masking sandboxing is added before load instructions.
106 # Test that address-masking sandboxing is added before store instructions.
168 # Test that address-masking sandboxing is added after instructions that change
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | nacl-mask.s | 4 # This test tests that address-masking sandboxing is added when given assembly
8 # Test that address-masking sandboxing is added before indirect branches and
36 # Test that address-masking sandboxing is added before load instructions.
106 # Test that address-masking sandboxing is added before store instructions.
168 # Test that address-masking sandboxing is added after instructions that change
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| /external/swiftshader/third_party/LLVM/test/Transforms/ScalarRepl/ |
| D | DifferingTypes.ll | 2 ; generated code should perform the appropriate masking operations required
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| /external/llvm/test/Analysis/ValueTracking/ |
| D | known-power-of-two.ll | 10 ; The next 3 lines prevent another fold from masking the bug.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ValueTracking/ |
| D | known-power-of-two.ll | 10 ; The next 3 lines prevent another fold from masking the bug.
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| /external/mesa3d/src/mesa/main/ |
| D | accum.c | 301 const GLboolean masking = (!ctx->Color.ColorMask[buffer][RCOMP] || in accum_return() local
307 if (masking) in accum_return()
337 if (masking) { in accum_return()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | shift-05.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-07.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-06.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-08.ll | 107 ; Check the next value up, which without masking must use a separate
149 ; Check the next value down, which without masking must use a separate
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-06.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-07.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-05.ll | 84 ; Check the next value up, which without masking must use a separate
117 ; Check the next value down, which without masking must use a separate
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| D | shift-08.ll | 107 ; Check the next value up, which without masking must use a separate
149 ; Check the next value down, which without masking must use a separate
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mad_int24.ll | 9 ; Make sure we aren't masking the inputs.
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| D | mul_int24.ll | 9 ; Make sure we are not masking the inputs
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | fix-vgpr-copies.mir | 1 # RUN: llc -march=amdgcn -start-after=greedy -disable-copyprop -stop-after=si-optimize-exec-masking…
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| D | mad_int24.ll | 9 ; Make sure we aren't masking the inputs.
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| /external/llvm/test/CodeGen/X86/ |
| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| D | simdlib_128_avx512_knights.inl | 32 // These use native AVX512 instructions with masking to enable a larger
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| D | simdlib_256_avx512_knights.inl | 32 // These use native AVX512 instructions with masking to enable a larger
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| /external/clang/lib/CodeGen/ |
| D | README.txt | 14 Bitfields accesses can be shifted to simplify masking and sign
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| /external/icu/icu4c/source/data/translit/ |
| D | Hebr_Latn.txt | 30 # move longer items here to avoid masking
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