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Searched refs:mvns (Results 1 – 25 of 52) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/
Dmvn.ll7 ; CHECK-NEXT: mvns r1, r1
20 ; CHECK-NEXT: mvns r3, r3
22 ; CHECK-NEXT: mvns r0, r2
39 ; CHECK-NEXT: mvns r2, r2
70 ; CHECK-NEXT: mvns r4, r4
72 ; CHECK-NEXT: mvns r3, r3
102 ; CHECK-NEXT: mvns r1, r1
115 ; CHECK-NEXT: mvns r3, r3
117 ; CHECK-NEXT: mvns r0, r2
134 ; CHECK-NEXT: mvns r2, r2
[all …]
Dconstants.ll24 ; CHECK-T1: mvns r5, r4
Dlong.ll44 ; CHECK: mvns r0, r0
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-mvn2.ll5 ; CHECK: mvns r0, r0
12 ; CHECK: mvns r0, r0
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-mvn2.ll5 ; CHECK: mvns r0, r0
12 ; CHECK: mvns r0, r0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dthumb2-mvn2.ll5 ; CHECK: mvns r0, r0
12 ; CHECK: mvns r0, r0
Difcvt-rescan-diamonds.ll26 ; CHECK-NEXT: mvns
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Darm_instructions.s54 @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
55 mvns r1,r2
Dbasic-thumb-instructions.s384 mvns r6, r3
386 @ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
Dbasic-arm-instructions.s991 mvns r3, #7
998 @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
1007 mvns r2, r3
1017 @ CHECK: mvns r2, r3 @ encoding: [0x03,0x20,0xf0,0xe1]
1031 mvns r5, r6, lsr r7
1036 @ CHECK: mvns r5, r6, lsr r7 @ encoding: [0x36,0x57,0xf0,0xe1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Darm_instructions.s61 @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
62 mvns r1,r2
Dbasic-thumb-instructions.s435 mvns r6, r3
437 @ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
/external/llvm/test/MC/ARM/
Darm_instructions.s61 @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
62 mvns r1,r2
Dbasic-thumb-instructions.s435 mvns r6, r3
437 @ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
/external/capstone/suite/MC/ARM/
Darm_instructions.s.cs17 0x02,0x10,0xf0,0xe1 = mvns r1, r2
Dbasic-thumb-instructions.s.cs87 0xde,0x43 = mvns r6, r3
Dbasic-arm-instructions.s.cs423 0x07,0x30,0xf0,0xe3 = mvns r3, #7
427 0x03,0x20,0xf0,0xe1 = mvns r2, r3
436 0x36,0x57,0xf0,0xe1 = mvns r5, r6, lsr r7
Dbasic-thumb2-instructions.s.cs514 0x7f,0xf0,0x15,0x08 = mvns r8, #21
516 0x7f,0xf0,0x7f,0x70 = mvns r0, #66846720
522 0xda,0x43 = mvns r2, r3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcmn.ll20 ; T1-NEXT: mvns r3, r0
Dminsize-imms.ll17 ; CHECK-V6M: mvns r0, [[TMP]] @ encoding: [0xc0,0x43]
/external/llvm/test/CodeGen/ARM/
Dminsize-imms.ll17 ; CHECK-V6M: mvns r0, [[TMP]] @ encoding: [0xc0,0x43]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt306 # CHECK: mvns r6, r3
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dthumb1.txt289 # CHECK: mvns r6, r3
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt306 # CHECK: mvns r6, r3
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-operand-rn-t32.cc57 M(mvns) \

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