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/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
DbinaryIntInstructions.3.2.ll25 ; CHECK: %res6 = add nuw i1 %x1, %x1
26 %res6 = add nuw i1 %x1, %x1
31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
32 %res8 = add nuw nsw i1 %x1, %x1
39 ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
40 %res1 = add nuw nsw <2 x i8> %x1, %x1
42 ; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2
43 %res2 = add nuw nsw <3 x i8> %x2, %x2
45 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
46 %res3 = add nuw nsw <4 x i8> %x3, %x3
[all …]
/external/llvm/test/Bitcode/
DbinaryIntInstructions.3.2.ll25 ; CHECK: %res6 = add nuw i1 %x1, %x1
26 %res6 = add nuw i1 %x1, %x1
31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
32 %res8 = add nuw nsw i1 %x1, %x1
39 ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
40 %res1 = add nuw nsw <2 x i8> %x1, %x1
42 ; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2
43 %res2 = add nuw nsw <3 x i8> %x2, %x2
45 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
46 %res3 = add nuw nsw <4 x i8> %x3, %x3
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dknownbits-recursion.ll27 %tmp10 = mul nuw nsw i32 %tmp9, %tmp9
29 %tmp12 = mul nuw nsw i32 %tmp11, %tmp11
31 %tmp14 = mul nuw nsw i32 %tmp13, %tmp13
33 %tmp16 = mul nuw nsw i32 %tmp15, %tmp15
35 %tmp18 = mul nuw nsw i32 %tmp17, %tmp17
37 %tmp20 = mul nuw nsw i32 %tmp19, %tmp19
39 %tmp22 = mul nuw nsw i32 %tmp21, %tmp21
41 %tmp24 = mul nuw nsw i32 %tmp23, %tmp23
43 %tmp26 = mul nuw nsw i32 %tmp25, %tmp25
45 %tmp28 = mul nuw nsw i32 %tmp27, %tmp27
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dconstantfold-shl-nuw-C-to-C.ll4 ; %r = shl nuw i8 C, %x
5 ; As per langref: If the nuw keyword is present, then the shift produces
14 %ret = shl nuw i8 -1, %x
15 ; nuw here means that %x can only be 0
23 %ret = shl nuw nsw i8 -1, %x
24 ; nuw here means that %x can only be 0
32 %ret = shl nuw i8 128, %x
47 ; CHECK-NEXT: [[RET:%.*]] = shl nuw i8 [[X]], [[Y:%.*]]
52 %ret = shl nuw i8 %x, %y
60 ; CHECK-NEXT: [[RET:%.*]] = shl nuw i8 [[X]], [[Y:%.*]]
[all …]
Dconstantfold-add-nuw-allones-to-allones.ll4 ; %ret = add nuw i8 %x, C
5 ; nuw means no unsigned wrap, from -1 to 0.
12 %ret = add nuw i8 %x, -1
13 ; nuw here means that %x can only be 0
21 %ret = add nuw nsw i8 %x, -1
22 ; nuw here means that %x can only be 0
30 %ret = add nuw i8 -1, %x ; swapped
31 ; nuw here means that %x can only be 0
45 ; CHECK-NEXT: [[RET:%.*]] = add nuw i8 [[X:%.*]], [[Y]]
50 %ret = add nuw i8 %x, %y
[all …]
/external/llvm/test/Assembler/
Dflags.ll7 ; CHECK: %z = add nuw i64 %x, %y
8 %z = add nuw i64 %x, %y
13 ; CHECK: %z = sub nuw i64 %x, %y
14 %z = sub nuw i64 %x, %y
19 ; CHECK: %z = mul nuw i64 %x, %y
20 %z = mul nuw i64 %x, %y
61 ; CHECK: %z = add nuw nsw i64 %x, %y
62 %z = add nuw nsw i64 %x, %y
67 ; CHECK: %z = sub nuw nsw i64 %x, %y
68 %z = sub nuw nsw i64 %x, %y
[all …]
/external/swiftshader/third_party/LLVM/test/Assembler/
Dflags.ll6 ; CHECK: %z = add nuw i64 %x, %y
7 %z = add nuw i64 %x, %y
12 ; CHECK: %z = sub nuw i64 %x, %y
13 %z = sub nuw i64 %x, %y
18 ; CHECK: %z = mul nuw i64 %x, %y
19 %z = mul nuw i64 %x, %y
60 ; CHECK: %z = add nuw nsw i64 %x, %y
61 %z = add nuw nsw i64 %x, %y
66 ; CHECK: %z = sub nuw nsw i64 %x, %y
67 %z = sub nuw nsw i64 %x, %y
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Assembler/
Dflags.ll7 ; CHECK: %z = add nuw i64 %x, %y
8 %z = add nuw i64 %x, %y
13 ; CHECK: %z = sub nuw i64 %x, %y
14 %z = sub nuw i64 %x, %y
19 ; CHECK: %z = mul nuw i64 %x, %y
20 %z = mul nuw i64 %x, %y
61 ; CHECK: %z = add nuw nsw i64 %x, %y
62 %z = add nuw nsw i64 %x, %y
67 ; CHECK: %z = sub nuw nsw i64 %x, %y
68 %z = sub nuw nsw i64 %x, %y
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopUnroll/ARM/
Dloop-unrolling.ll16 ; CHECK-UNROLL-A: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
17 ; CHECK-UNROLL-A: [[IV2]] = add nuw nsw i32 [[IV1]], 1
22 ; CHECK-UNROLL-T1: [[IV1]] = add nuw nsw i32 [[IV0]], 1
27 ; CHECK-UNROLL-T2: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
28 ; CHECK-UNROLL-T2: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
29 ; CHECK-UNROLL-T2: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
30 ; CHECK-UNROLL-T2: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1
31 ; CHECK-UNROLL-T2: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1
32 ; CHECK-UNROLL-T2: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1
33 ; CHECK-UNROLL-T2: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1
[all …]
/external/llvm/test/Transforms/LoadCombine/
Dload-combine.ll11 %4 = shl nuw i64 %3, 56
15 %8 = shl nuw nsw i64 %7, 48
20 %13 = shl nuw nsw i64 %12, 40
25 %18 = shl nuw nsw i64 %17, 32
30 %23 = shl nuw nsw i64 %22, 24
35 %28 = shl nuw nsw i64 %27, 16
40 %33 = shl nuw nsw i64 %32, 8
58 %5 = shl nuw i32 %4, 16
74 %5 = shl nuw i32 %4, 16
90 %5 = shl nuw i32 %4, 16
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dload-combine.ll16 %tmp7 = shl nuw nsw i32 %tmp6, 8
21 %tmp12 = shl nuw nsw i32 %tmp11, 16
26 %tmp17 = shl nuw nsw i32 %tmp16, 24
44 %tmp7 = shl nuw nsw i32 %tmp6, 8
49 %tmp12 = shl nuw nsw i32 %tmp11, 16
54 %tmp17 = shl nuw nsw i32 %tmp16, 24
69 %tmp3 = shl nuw nsw i32 %tmp2, 24
73 %tmp7 = shl nuw nsw i32 %tmp6, 16
78 %tmp12 = shl nuw nsw i32 %tmp11, 8
99 %tmp6 = shl nuw nsw i64 %tmp5, 8
[all …]
Dload-combine-big-endian.ll12 %tmp3 = shl nuw nsw i32 %tmp2, 24
16 %tmp7 = shl nuw nsw i32 %tmp6, 16
21 %tmp12 = shl nuw nsw i32 %tmp11, 8
42 %tmp6 = shl nuw nsw i16 %tmp2, 8
50 %tmp14 = shl nuw nsw i16 %tmp10, 8
54 %tmp18 = shl nuw nsw i32 %tmp16, 16
71 %tmp6 = shl nuw nsw i32 %tmp2, 16
87 %tmp4 = shl nuw nsw i32 %tmp3, 16
91 %tmp8 = shl nuw nsw i32 %tmp7, 8
113 %tmp6 = shl nuw nsw i64 %tmp5, 8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dload-combine.ll29 %tmp7 = shl nuw nsw i32 %tmp6, 8
34 %tmp12 = shl nuw nsw i32 %tmp11, 16
39 %tmp17 = shl nuw nsw i32 %tmp16, 24
61 %tmp7 = shl nuw nsw i32 %tmp6, 8
66 %tmp12 = shl nuw nsw i32 %tmp11, 16
71 %tmp17 = shl nuw nsw i32 %tmp16, 24
96 %tmp3 = shl nuw nsw i32 %tmp2, 24
100 %tmp7 = shl nuw nsw i32 %tmp6, 16
105 %tmp12 = shl nuw nsw i32 %tmp11, 8
132 %tmp6 = shl nuw nsw i64 %tmp5, 8
[all …]
Dload-combine-big-endian.ll17 %tmp3 = shl nuw nsw i32 %tmp2, 24
21 %tmp7 = shl nuw nsw i32 %tmp6, 16
26 %tmp12 = shl nuw nsw i32 %tmp11, 8
59 %tmp7 = shl nuw nsw i32 %tmp6, 8
64 %tmp12 = shl nuw nsw i32 %tmp11, 16
69 %tmp17 = shl nuw nsw i32 %tmp16, 24
90 %tmp6 = shl nuw nsw i16 %tmp2, 8
98 %tmp14 = shl nuw nsw i16 %tmp10, 8
102 %tmp18 = shl nuw nsw i32 %tmp16, 16
123 %tmp6 = shl nuw nsw i32 %tmp2, 16
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Djumbled-load-used-in-phi.ll59 ; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
61 ; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
63 ; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
74 ; CHECK-NEXT: [[TMP9:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
76 ; CHECK-NEXT: [[TMP10:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
78 ; CHECK-NEXT: [[TMP11:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
89 ; CHECK-NEXT: [[TMP15:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
91 ; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
93 ; CHECK-NEXT: [[TMP17:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
104 ; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
[all …]
/external/llvm/test/Transforms/LoopVectorize/AArch64/
Dloop-vectorization-factors.ll8 ; CHECK: add nuw nsw <16 x i8>
24 %add = add nuw nsw i32 %conv, 2
28 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
36 ; CHECK: add nuw nsw <8 x i16>
52 %add = add nuw nsw i32 %conv8, 2
56 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
64 ; CHECK: add nuw nsw <8 x i16>
80 %add = add nuw nsw i32 %conv, 2
84 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
110 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dselect-obo-peo-ops.ll7 ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
15 %2 = shl nuw nsw i32 %1, 2
26 ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
34 %2 = shl nuw i32 %1, 2
45 ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
64 ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
83 ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
91 %2 = shl nuw nsw i32 %1, 2
102 ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
110 %2 = shl nuw i32 %1, 2
[all …]
Dicmp-shl-nuw.ll9 %c = shl nuw i64 %0, 32
19 %c = shl nuw i128 %0, 64
29 %c = shl nuw i64 %0, 16
39 %c = shl nuw <2 x i64> %0, <i64 16, i64 16>
49 %c = shl nuw <2 x i64> %0, <i64 16, i64 16>
59 %c = shl nuw <2 x i64> %0, <i64 12, i64 12>
69 %c = shl nuw i64 %0, 8
79 %c = shl nuw <2 x i16> %0, <i16 8, i16 8>
89 %c = shl nuw <2 x i32> %0, <i32 16, i32 16>
Dset-lowbits-mask-canonicalize.ll45 %ret = add nuw i32 %setbit, -1
54 %ret = add nuw nsw i32 %setbit, -1
87 %ret = add nuw i32 %setbit, -1
96 %ret = add nuw nsw i32 %setbit, -1
100 ; shl is nuw
108 %setbit = shl nuw i32 1, %NBits
119 %setbit = shl nuw i32 1, %NBits
128 %setbit = shl nuw i32 1, %NBits
129 %ret = add nuw i32 %setbit, -1
137 %setbit = shl nuw i32 1, %NBits
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dload-combine.ll26 %tmp6 = shl nuw nsw i32 %tmp5, 8
31 %tmp11 = shl nuw nsw i32 %tmp10, 16
36 %tmp16 = shl nuw nsw i32 %tmp15, 24
70 %tmp3 = shl nuw nsw i32 %tmp2, 24
74 %tmp7 = shl nuw nsw i32 %tmp6, 16
79 %tmp12 = shl nuw nsw i32 %tmp11, 8
107 %tmp6 = shl nuw nsw i32 %tmp5, 16
133 %tmp7 = shl nuw nsw i32 %tmp6, 16
137 %tmp11 = shl nuw nsw i32 %tmp10, 24
163 %tmp6 = shl nuw nsw i16 %tmp5, 8
[all …]
Dlrshrink.ll4 ; Checks if "%7 = add nuw nsw i64 %4, %2" is moved before the last call
34 %7 = add nuw nsw i64 %0, %r
36 %8 = add nuw nsw i64 %2, %7
37 %9 = add nuw nsw i64 %4, %8
38 %10 = add nuw nsw i64 %6, %9
39 %11 = add nuw nsw i64 %s, %t
41 %12 = add nuw nsw i64 %10, %11
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopUnrollAndJam/
Ddependencies.ll28 %add6 = add nuw nsw i32 %j, 1
33 %add7 = add nuw nsw i32 %i, 1
34 %add72 = add nuw nsw i32 %i, -1
68 %add6 = add nuw nsw i32 %j, 1
73 %add7 = add nuw nsw i32 %i, 1
74 %add72 = add nuw nsw i32 %i, 0
106 %add6 = add nuw nsw i32 %j, 1
111 %add7 = add nuw nsw i32 %i, 1
112 %add72 = add nuw nsw i32 %i, 1
146 %add72 = add nuw nsw i32 %i, -1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/
Dpr35836.ll13 %add = add nuw nsw i64 %ll.0100, 0
14 %add3 = add nuw nsw i64 %add, 0
18 %add10 = add nuw nsw i64 %conv9, %conv7
19 %add11 = add nuw nsw i64 %add10, %shr
23 %add19 = add nuw nsw i64 %conv18, %conv16
24 %add20 = add nuw nsw i64 %add19, %shr14
32 %add28 = add nuw nsw i64 %conv27, %conv25
33 %add29 = add nuw nsw i64 %add28, %shr23
/external/llvm/test/Transforms/Reassociate/
Dwrap-flags.ll17 ; CHECK: %mul = mul nuw i32 %i, 4
21 %mul = shl nuw i32 %i, 2
27 ; CHECK: %mul = mul nuw nsw i32 %i, 4
31 %mul = shl nuw nsw i32 %i, 2
42 %add = add nuw i2 %X1, 1
43 %sub = sub nuw nsw i2 %X2, %add
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/
Dwrap-flags.ll17 ; CHECK: %mul = mul nuw i32 %i, 4
21 %mul = shl nuw i32 %i, 2
27 ; CHECK: %mul = mul nuw nsw i32 %i, 4
31 %mul = shl nuw nsw i32 %i, 2
42 %add = add nuw i2 %X1, 1
43 %sub = sub nuw nsw i2 %X2, %add

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