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/external/libxcam/cl_kernel/
Dkernel_wavelet_haar.cl51 line_ll = (row_l.odd + row_l.even) / 2.0f;
52 line_hl = (row_l.odd - row_l.even) / 2.0f;
53 line_lh = (row_h.odd + row_h.even) / 2.0f;
54 line_hh = (row_h.odd - row_h.even) / 2.0f;
59 line_ll.odd = (row_l.odd.odd + row_l.odd.even) / 2.0f;
60 line_hl.odd = (row_l.odd.odd - row_l.odd.even) / 2.0f;
61 line_lh.odd = (row_h.odd.odd + row_h.odd.even) / 2.0f;
62 line_hh.odd = (row_h.odd.odd - row_h.odd.even) / 2.0f;
65 line_ll.even = (row_l.even.odd + row_l.even.even) / 2.0f;
66 line_hl.even = (row_l.even.odd - row_l.even.even) / 2.0f;
[all …]
Dkernel_defog_dcp.cl32 uv_r.even = -0.001f * uv.even + 1.402f * uv.odd;
33 uv_r.odd = uv_r.even;
34 uv_g.even = -0.344f * uv.even - 0.714f * uv.odd;
35 uv_g.odd = uv_g.even;
36 uv_b.even = 1.772f * uv.even + 0.001f * uv.odd;
37 uv_b.odd = uv_b.even;
127 r = (in_r[0].even + in_r[0].odd + in_r[1].even + in_r[1].odd) * 0.25f;
128 g = (in_g[0].even + in_g[0].odd + in_g[1].even + in_g[1].odd) * 0.25f;
129 b = (in_b[0].even + in_b[0].odd + in_b[1].even + in_b[1].odd) * 0.25f;
131 out_data.odd = (0.5f * r - 0.419f * g - 0.081f * b) + 128.0f;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dbuiltins-ppc-p9-f128.ll12 %0 = call fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128 %a)
19 declare fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128)
23 %0 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %c)
26 %1 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %sub)
28 %2 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %c)
32 %3 = call fp128 @llvm.ppc.fmaf128.round.to.odd(fp128 %a, fp128 %b, fp128 %sub2)
44 declare fp128 @llvm.ppc.fmaf128.round.to.odd(fp128, fp128, fp128)
48 %0 = call fp128 @llvm.ppc.addf128.round.to.odd(fp128 %a, fp128 %b)
55 declare fp128 @llvm.ppc.addf128.round.to.odd(fp128, fp128)
59 %0 = call fp128 @llvm.ppc.subf128.round.to.odd(fp128 %a, fp128 %b)
[all …]
/external/llvm/test/MC/Mips/
Dupdate-module-level-options.s6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dset-oddspreg-nooddspreg-error.s6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dnooddspreg-error.s9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dupdate-module-level-options.s6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dset-oddspreg-nooddspreg-error.s6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dnooddspreg-error.s9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
/external/eigen/Eigen/src/Geometry/
DEulerAngles.h48 const Index odd = ((a0+1)%3 == a1) ? 0 : 1; in eulerAngles() local
50 const Index j = (a0 + 1 + odd)%3; in eulerAngles()
51 const Index k = (a0 + 2 - odd)%3; in eulerAngles()
56 if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0))) in eulerAngles()
91 if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0))) { in eulerAngles()
106 if (!odd) in eulerAngles()
/external/mesa3d/src/gallium/auxiliary/util/
Du_pwr8.h78 vec_unpacklo_epi32 (__m128i even, __m128i odd) in vec_unpacklo_epi32() argument
87 return vec_perm (even, odd, perm_mask); in vec_unpacklo_epi32()
91 vec_unpackhi_epi32 (__m128i even, __m128i odd) in vec_unpackhi_epi32() argument
100 return vec_perm (even, odd, perm_mask); in vec_unpackhi_epi32()
104 vec_unpacklo_epi64 (__m128i even, __m128i odd) in vec_unpacklo_epi64() argument
113 return vec_perm (even, odd, perm_mask); in vec_unpacklo_epi64()
117 vec_unpackhi_epi64 (__m128i even, __m128i odd) in vec_unpackhi_epi64() argument
126 return vec_perm (even, odd, perm_mask); in vec_unpackhi_epi64()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUNopFiller.cpp60 odd = 3 } SPUOpPlace; enumerator
93 if( isEvenPlace && this_optype == odd && next_optype == even ) { in runOnMachineBasicBlock()
102 else if ( !isEvenPlace && this_optype == even && next_optype == odd){ in runOnMachineBasicBlock()
119 if (getOpPlacement( *J ) == odd) { in runOnMachineBasicBlock()
146 case 1: retval = odd; break; in getOpPlacement()
/external/python/cpython2/Modules/zlib/
Dcrc32.c380 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ local
387 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */
390 odd[n] = row;
395 gf2_matrix_square(even, odd);
398 gf2_matrix_square(odd, even);
404 gf2_matrix_square(even, odd);
414 gf2_matrix_square(odd, even);
416 crc1 = gf2_matrix_times(odd, crc1);
/external/zlib/src/
Dcrc32.c380 unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ local
387 odd[0] = 0xedb88320UL; /* CRC-32 polynomial */
390 odd[n] = row;
395 gf2_matrix_square(even, odd);
398 gf2_matrix_square(odd, even);
404 gf2_matrix_square(even, odd);
414 gf2_matrix_square(odd, even);
416 crc1 = gf2_matrix_times(odd, crc1);
/external/clang/test/Analysis/
DNewDelete-path-notes.cpp23 void test(Odd *odd) { in test() argument
24 odd->kill(); // expected-note{{Calling 'Odd::kill'}} in test()
26 delete odd; // expected-warning {{Attempt to free released memory}} in test()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll12 ; Force the float into an odd-numbered register using named registers and
19 ; The intention is that if odd single precision registers are permitted, the
23 ; On the other hand, if odd single precision registers are not permitted, it
46 ; Force the float into an odd-numbered register using named registers and
53 ; The intention is that if odd single precision registers are permitted, the
57 ; On the other hand, if odd single precision registers are not permitted, it
85 ; The intention is that if odd single precision registers are permitted, the
88 ; On the other hand, if odd single precision registers are not permitted, it
113 ; The intention is that if odd single precision registers are permitted, the
116 ; On the other hand, if odd single precision registers are not permitted, it
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll12 ; Force the float into an odd-numbered register using named registers and
19 ; The intention is that if odd single precision registers are permitted, the
23 ; On the other hand, if odd single precision registers are not permitted, it
46 ; Force the float into an odd-numbered register using named registers and
53 ; The intention is that if odd single precision registers are permitted, the
57 ; On the other hand, if odd single precision registers are not permitted, it
85 ; The intention is that if odd single precision registers are permitted, the
88 ; On the other hand, if odd single precision registers are not permitted, it
113 ; The intention is that if odd single precision registers are permitted, the
116 ; On the other hand, if odd single precision registers are not permitted, it
/external/pdfium/fxbarcode/oned/
DBC_OnedEANChecksum.cpp10 int32_t odd = 0; in EANCalcChecksum() local
15 odd += FXSYS_DecimalCharToInt(contents[i - 1]); in EANCalcChecksum()
20 return (10 - (odd * 3 + even) % 10) % 10; in EANCalcChecksum()
/external/selinux/secilc/docs/
Dcil_xen_statements.md25 <tr class="odd">
35 <tr class="odd">
65 <tr class="odd">
75 <tr class="odd">
105 <tr class="odd">
113 <tr class="odd">
143 <tr class="odd">
151 <tr class="odd">
181 <tr class="odd">
189 <tr class="odd">
Dcil_user_statements.md21 <tr class="odd">
57 <tr class="odd">
65 <tr class="odd">
99 <tr class="odd">
135 <tr class="odd">
143 <tr class="odd">
193 <tr class="odd">
201 <tr class="odd">
239 <tr class="odd">
247 <tr class="odd">
[all …]
Dcil_role_statements.md21 <tr class="odd">
59 <tr class="odd">
67 <tr class="odd">
101 <tr class="odd">
137 <tr class="odd">
145 <tr class="odd">
201 <tr class="odd">
209 <tr class="odd">
237 <tr class="odd">
245 <tr class="odd">
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/PowerPC/
Dstride-vectorization.ll19 %odd.idx = add nsw i64 %0, 1
22 %arrayidx.odd = getelementptr inbounds double, double* %b, i64 %odd.idx
25 %2 = load double, double* %arrayidx.odd, align 8
/external/llvm/test/Transforms/LoopVectorize/PowerPC/
Dstride-vectorization.ll19 %odd.idx = add nsw i64 %0, 1
22 %arrayidx.odd = getelementptr inbounds double, double* %b, i64 %odd.idx
25 %2 = load double, double* %arrayidx.odd, align 8
/external/libvpx/libvpx/vpx_dsp/ppc/
Dbitdepth_conversion_vsx.h37 const int32x4_t odd = vec_mulo(v, one); in store_tran_low() local
38 const int32x4_t high = vec_mergeh(even, odd); in store_tran_low()
39 const int32x4_t low = vec_mergel(even, odd); in store_tran_low()
/external/skia/src/compute/skc/
Dmacros.h60 SKC_EXPAND_X(1, 1,.s1,SKC_EMPTY,.odd)
64 SKC_EXPAND_X(1, 1,.s1,SKC_COMMA,.odd.even) \
65 SKC_EXPAND_X(2, 2,.s2,SKC_COMMA,.even.odd) \
66 SKC_EXPAND_X(3, 3,.s3,SKC_EMPTY,.odd.odd)

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