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Searched refs:output_hz (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3036.c52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() local
57 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
59 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
Dclk_rk322x.c49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() local
53 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
55 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
Dclk_rk3188.c92 uint output_hz = vco_hz / div->no; in rkclk_set_pll() local
95 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
97 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && in rkclk_set_pll()
Dclk_rk3128.c46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() local
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
52 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); in rkclk_set_pll()
Dclk_rk3288.c150 uint output_hz = vco_hz / div->no; in rkclk_set_pll() local
153 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
155 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && in rkclk_set_pll()
Dclk_rk3368.c94 uint output_hz = vco_hz / div->no; in rkclk_set_pll() local
97 pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()