Searched refs:pad_ctrl (Results 1 – 7 of 7) sorted by relevance
31 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; in imx_iomux_v3_setup_pad() local35 if (pad_ctrl & PAD_CTL_LVE) { in imx_iomux_v3_setup_pad()36 pad_ctrl &= ~PAD_CTL_LVE; in imx_iomux_v3_setup_pad()37 pad_ctrl |= PAD_CTL_LVE_BIT; in imx_iomux_v3_setup_pad()69 if (!(pad_ctrl & NO_PAD_CTRL)) in imx_iomux_v3_setup_pad()70 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl, in imx_iomux_v3_setup_pad()73 if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) in imx_iomux_v3_setup_pad()74 __raw_writel(pad_ctrl, base + pad_ctrl_ofs); in imx_iomux_v3_setup_pad()76 else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) in imx_iomux_v3_setup_pad()
31 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; in mx7ulp_iomux_setup_pad() local35 pad_ctrl_ofs, pad_ctrl); in mx7ulp_iomux_setup_pad()51 if (!(pad_ctrl & NO_PAD_CTRL)) in mx7ulp_iomux_setup_pad()54 (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)), in mx7ulp_iomux_setup_pad()
62 sel_input, pad_ctrl) \ argument65 ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
69 sel_input, pad_ctrl) \ argument73 ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
889 u32 pad_ctrl = 0; in tegra_dc_sor_power_down_unused_lanes() local894 pad_ctrl = DP_PADCTL_PD_TXD_0_NO | in tegra_dc_sor_power_down_unused_lanes()900 pad_ctrl = DP_PADCTL_PD_TXD_0_NO | in tegra_dc_sor_power_down_unused_lanes()906 pad_ctrl = DP_PADCTL_PD_TXD_0_NO | in tegra_dc_sor_power_down_unused_lanes()916 pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN; in tegra_dc_sor_power_down_unused_lanes()917 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); in tegra_dc_sor_power_down_unused_lanes()
104 u32 pad_ctrl; member
35 writel(pad_ctl, &ddr2_phy->pad_ctrl); in ddr2_phy_init()