Searched refs:pdiv3 (Results 1 – 3 of 3) sorted by relevance
37 u32 pdiv3; member
98 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3); in setup_clock_synthesizer()
607 .pdiv3 = 0x2,663 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ in board_init()