| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sunxi_dw.c | 33 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
51 setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
433 clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); in mctl_channel_init()
435 setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26)); in mctl_channel_init()
437 clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); in mctl_channel_init()
465 setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); in mctl_channel_init()
469 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
472 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
476 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), in mctl_channel_init()
480 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
[all …]
|
| D | dram_sun9i.c | 735 clrsetbits_le32(&mctl_phy->pgcr[1], in mctl_channel_init()
746 clrbits_le32(&mctl_phy->pgcr[0], 0x3f); in mctl_channel_init()
810 clrbits_le32(&mctl_phy->pgcr[3], (1 << 25)); in mctl_channel_init()
|
| D | dram_sun6i.c | 121 writel(MCTL_PGCR, &mctl_phy->pgcr); in mctl_channel_init()
167 clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); in mctl_channel_init()
|
| /external/u-boot/board/renesas/sh7753evb/ |
| D | sh7753evb.c | 34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ in init_gpio()
93 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); in init_gether_mdio()
182 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); in board_mmc_init()
|
| /external/u-boot/board/renesas/sh7752evb/ |
| D | sh7752evb.c | 86 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); in init_gether_mdio()
166 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); in board_mmc_init()
|
| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk3288.c | 319 clrsetbits_le32(&publ->pgcr, 0x1F, in phy_cfg()
340 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
487 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
527 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
639 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_rank_bw_detect()
861 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_init()
|
| D | sdram_rk3188.c | 282 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
429 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
469 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
586 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_rank_bw_detect()
762 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_init()
|
| /external/u-boot/arch/sh/include/asm/ |
| D | cpu_sh7752.h | 107 unsigned short pgcr; member
|
| D | cpu_sh7753.h | 107 unsigned short pgcr; member
|
| /external/u-boot/drivers/ram/stm32mp1/ |
| D | stm32mp1_ddr.h | 117 u32 pgcr; member
|
| D | stm32mp1_ddr_regs.h | 143 u32 pgcr; /* 0x08 R/W PHY General Configuration*/ member
|
| D | stm32mp1_ddr.c | 125 DDRPHY_REG_REG(pgcr),
|
| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | dram_sunxi_dw.h | 112 u32 pgcr[4]; /* 0x100 PHY general configuration registers */ member
|
| D | dram_sun9i.h | 95 u32 pgcr[4]; /* 0x08 PHY general configuration register */ member
|
| D | dram_sun6i.h | 159 u32 pgcr; /* 0x08 phy general configuration register */ member
|
| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | ddr_rk3288.h | 169 u32 pgcr; member
|