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Searched refs:phy_read (Results 1 – 25 of 47) sorted by relevance

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/external/u-boot/drivers/net/phy/
Dmarvell.c109 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
113 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
122 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
158 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
176 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
227 reg = phy_read(phydev, in m88e1111s_config()
243 reg = phy_read(phydev, in m88e1111s_config()
258 reg = phy_read(phydev, in m88e1111s_config()
270 reg = phy_read(phydev, in m88e1111s_config()
276 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
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Dvitesse.c89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
149 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
177 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); in vsc8574_config()
194 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
197 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
202 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON); in vsc8574_config()
222 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); in vsc8514_config()
237 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
240 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
250 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23); in vsc8514_config()
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Dmscc.c149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
177 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
183 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
204 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG); in mscc_parse_status()
253 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
256 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
259 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
314 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
326 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
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Dphy.c48 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
81 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
93 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
155 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
195 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
230 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
265 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
271 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
293 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_parse_link()
307 gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); in genphy_parse_link()
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Dgeneric_10g.c42 phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
43 reg = phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
59 stat2 = phy_read(phydev, mmd, MDIO_STAT2); in gen10g_discover_mmds()
65 devs1 = phy_read(phydev, mmd, MDIO_DEVS1); in gen10g_discover_mmds()
66 devs2 = phy_read(phydev, mmd, MDIO_DEVS2); in gen10g_discover_mmds()
Daquantia.c24 u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
69 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
70 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
76 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
88 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
89 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
95 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_startup()
Drealtek.c93 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
107 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG); in rtl8211x_config()
117 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); in rtl8211x_config()
132 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); in rtl8211f_config()
163 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); in rtl8211x_parse_status()
182 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211x_parse_status()
222 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS); in rtl8211f_parse_status()
235 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_parse_status()
Dbroadcom.c45 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
69 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); in bcm54xx_parse_status()
129 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; in bcm5482_read_wirespeed()
137 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
236 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); in bcm5482_is_serdes()
272 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); in bcm5482_parse_serdes_sr()
Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
Dmeson-gxl.c62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in meson_gxl_startup()
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in meson_gxl_startup()
70 exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION); in meson_gxl_startup()
Dxilinx_phy.c49 status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in xilinxphy_startup()
71 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
120 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_config()
Dnatsemi.c23 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
67 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); in dp83865_parse_status()
120 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
Dteranetics.c30 phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf; in tn2020_config()
57 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT); in tn2020_startup()
Dmicrel_ksz90x1.c51 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
229 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); in ksz9021_phy_extended_read()
314 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA); in ksz9031_phy_extended_read()
354 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in ksz9031_config()
Dti.c130 value = phy_read(phydev, addr, MII_MMD_DATA); in phy_read_mmd_indirect()
231 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); in dp83867_config()
245 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2); in dp83867_config()
Datheros.c62 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8035_config()
66 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8035_config()
Dcortina.c240 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
256 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
291 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); in cs4223_phy_init()
Dmicrel_ksz8xxx.c34 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
67 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
/external/u-boot/board/gdsys/a38x/
Dihs_phys.c33 reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); in ihs_phy_config()
41 reg = phy_read(phydev, MDIO_DEVAD_NONE, 26); in ihs_phy_config()
51 reg = phy_read(phydev, MDIO_DEVAD_NONE, 4); in ihs_phy_config()
54 reg = phy_read(phydev, MDIO_DEVAD_NONE, 9); in ihs_phy_config()
59 reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); in ihs_phy_config()
/external/u-boot/board/compulab/cl-som-imx7/
Dcl-som-imx7.c138 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
147 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
154 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in cl_som_imx7_rgmii_rework()
/external/u-boot/board/spear/x600/
Dx600.c76 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
77 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
/external/u-boot/board/Marvell/db-mv784mp-gp/
Ddb-mv784mp-gp.c102 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); in board_phy_config()
111 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); in board_phy_config()
/external/u-boot/board/congatec/cgtqmx6eval/
Dcgtqmx6eval.c282 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_eth_init()
283 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_eth_init()
331 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in mx6_rgmii_rework()
332 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in mx6_rgmii_rework()
372 val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA); in mx6_rgmii_rework()
379 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in mx6_rgmii_rework()
385 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in mx6_rgmii_rework()
/external/u-boot/board/k+p/kp_imx6q_tpc/
Dkp_imx6q_tpc.c144 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8031_phy_fixup()
151 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8031_phy_fixup()
/external/u-boot/board/technexion/pico-imx7d/
Dpico-imx7d.c196 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in board_phy_config()
203 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in board_phy_config()

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