Searched refs:physSPReg (Results 1 – 2 of 2) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 11790 physSPReg = Is64Bit ? X86::RSP : X86::ESP; in EmitLoweredSegAlloca() local
11805 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); in EmitLoweredSegAlloca()
11815 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) in EmitLoweredSegAlloca()
11828 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) in EmitLoweredSegAlloca()
11836 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) in EmitLoweredSegAlloca()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 27444 physSPReg = in EmitLoweredSegAlloca() local
27459 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); in EmitLoweredSegAlloca()
27469 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) in EmitLoweredSegAlloca()
27495 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) in EmitLoweredSegAlloca()
27505 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) in EmitLoweredSegAlloca()
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